Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.6.4.6.8. Dynamic Reconfiguration Interface

You can use the dynamic reconfiguration interface signals to dynamically change between 1G and 10G data rates.
Table 142.  Dynamic Reconfiguration Interface Signals
Signal Name Direction Clock Domain Description
rc_busy Output Synchronous to mgmt_clk When asserted, indicates that reconfiguration is in progress. Synchronous to the mgmt_clk. This signal is only exposed under the following condition:
  • Turn on Enable internal PCS reconfiguration logic
start_pcs_reconfig Input Synchronous to mgmt_clk When asserted, initiates reconfiguration of the PCS. Sampled with the mgmt_clk. This signal is only exposed under the following condition:
  • Turn on Enable internal PCS reconfiguration logic
mode_1g_10gbar Input Synchronous to mgmt_clk This signal selects either the 1G or 10G tx-parallel-data going to the PCS. It is only used for the 1G/10G application (variant) under the following circumstances:
  • the Sequencer (auto-rate detect) is not enabled
  • 1G mode is enabled

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