Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

7.4.1.1. User Recalibration

User recalibration requires access to the internal configuration bus and calibration registers through the Avalon® memory-mapped interface reconfiguration. Follow the steps below to perform a user recalibration.

  1. Proceed to the next step if ATX PLL is not used in your application, otherwise perform the ATX PLL calibration process:
    1. Request access to the internal configuration bus by writing 0x2 to offset address 0x0[7:0].
    2. Wait for reconfig_waitrequest to deassert (logic low), or wait until capability register of PreSICE Avalon® memory-mapped interface control 0x280[2]=0x0.
    3. Read-Modify-Write 0x1 to the offset address 0x100[0] of the ATX PLL.
    4. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0].
    5. Periodically check the *cal_busy output signals or read the capability registers 0x280[1] to check *cal_busy status until calibration is complete.
    If you are recalibrating your ATX PLL and have adjacent ATX PLL used on the same side of the device, follow the ATX PLL-to-ATX PLL spacing guideline as stated in the "Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" chapter.
  2. Proceed to the next step if fPLL is not used in your application, otherwise perform the fPLL user recalibration process:
    1. Access the internal configuration bus by writing 0x2 to offset address 0x0[7:0].
    2. Wait for reconfig_waitrequest to deassert (logic low), or wait until capability register of PreSICE Avalon® memory-mapped interface control 0x280[2]=0x0.
    3. Read-Modify-Write 0x1 to the offset address 0x100[1] of the fPLL.
    4. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0].
    5. Periodically check the *cal_busy output signals or read the capability registers 0x280[1] to check *cal_busy status until calibration is complete.
    If you are recalibrating your fPLL and have ATX PLL used on the same side of the device, follow the fPLL-to-ATX PLL spacing guideline as stated in the "Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" chapter.
  3. Perform the PMA user recalibration process:
    1. Request access to the internal configuration bus by writing 0x2 to offset address 0x0[7:0].
    2. Wait for reconfig_waitrequest to deassert (logic low), or wait until capability register of PreSICE Avalon® memory-mapped interface control 0x281[2]=0x0.
    3. Configure the PMA calibration enable register 0x100. You must set 0x0 to 0x100[6] to enable any calibration.
      • Read-Modify-Write 0x1 to 0x100[1] to start PMA RX calibration.
      • Read-Modify-Write 0x1 to 0x100[5] to start PMA TX calibration.
    4. Do Read-Modify-Write on the rate switch flag register if you switched rates with a different CDR bandwidth setting.
    5. Do Read-Modify-Write on 0x281[5:4] to disable/enable rx_cal_busy and tx_cal_busy.
      • To enable rx_cal_busy, write 0x1 to 0x281[5].
      • To disable rx_cal_busy, write 0x0 to 0x281[5].
      • To enable tx_cal_busy, write 0x1 to 0x281[4].
      • To disable tx_cal_busy, write 0x0 to 0x281[4].
    6. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0].
    7. Perform a loop to check the tx_cal_busy and rx_cal_busy output signals or read the capability registers 0x281[1:0] to check *cal_busy status until calibration is complete.

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