Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.7.13. PHY IP Core for PCIe* (PIPE) Link Equalization for Gen3 Data Rate

Gen3 mode requires TX and RX link equalization because of the data rate, the channel characteristics, receiver design, and process variations. The link equalization process allows the Endpoint and Root Port to adjust the TX and RX setup of each lane to improve signal quality. This process results in Gen3 links with a receiver Bit Error Rate (BER) that is less than 10-12.

For detailed information about the four-stage link equalization procedure for 8.0 GT/s data rate, refer to Section 4.2.3 in the PCI Express* Base Specification, Rev 3.0. A new LTSSM state, Recovery.Equalization with Phases 0–3, reflects progress through Gen3 equalization. Phases 2 and 3 of link equalization are optional. Each link must progress through all four phases, even if no adjustments occur. If you skip Phases 2 and 3, you speed up link training at the expense of link BER optimization.

Phase 0

Phase 0 includes the following steps:

  1. The upstream component enters Phase 0 of equalization during Recovery.Rcvrconfig by sending EQ TS2 training sets with starting presets for the downstream component. EQ TS2 training sets may be sent at 2.5 GT/s or 5 GT/s.
  2. The downstream component enters Phase 0 of equalization after exiting Recovery.Speed at 8 GT/s. It receives the starting presets from the training sequences and applies them to its transmitter. At this time, the upstream component has entered Phase 1 and is operating at 8 GT/s.
  3. To move to Phase 1, the receiver must have a BER < 10-4. The receiver should be able to decode enough consecutive training sequences.
  4. In order to move to Equalization Phase 1, the downstream component must detect training sets with Equalization Control (EC) bits set to 2’b01.

Phase 1

During Phase 1 of the equalization process, the link partners exchange Full Swing (FS) and Low Frequency (LF) information. These values represent the upper and lower bounds for the TX coefficients. The receiver uses this information to calculate and request the next set of transmitter coefficients.

  1. The upstream component moves to EQ Phase 2 when training sets with EC bits set to 1’b0 are captured on all lanes. It also sends EC=2’b10, starting pre-cursor, main cursor, and post-cursor coefficients.
  2. The downstream component moves to EQ Phase 2 after detecting these new training sets.
Use the pipe_g3_txdeemph[17:0] port to select the transmitter de-emphasis. The 18 bits specify the following coefficients:
  • [5:0]: C-1
  • [11:6]: C0
  • [17:12]: C+1

Refer to Preset Mappings to TX De-emphasis for the mapping between presets and TX de-emphasis.

Phase 2 (Optional)

During Phase 2, the Endpoint tunes the TX coefficients of the Root Port. The TS1 Use Preset bit determines whether the Endpoint uses presets for coarse resolution or coefficients for fine resolution.

If you are using the PHY IP Core for PCI Express (PIPE) as the Root Port, the Endpoint can tune the Root Port TX coefficients.

The tuning sequence typically includes the following steps:

  1. The Endpoint receives the starting presets from the Phase 2 training sets sent by the Root Port.
  2. The circuitry in the Endpoint receiver determines the BER. It calculates the next set of transmitter coefficients using FS and LF. It also embeds this information in the Training Sets for the Link Partner to apply to its transmitter.
    The Root Port decodes these coefficients and presets, performs legality checks for the three transmitter coefficient rules and applies the settings to its transmitter and also sends them in the Training Sets. The default Full Swing (FS) value advertised by the Intel® device is 60 and Low Frequency (LF) is 20. The three rules for transmitter coefficients are:
    1. |C-1| <= Floor (FS/4)
    2. |C-1|+C0+|C+1| = FS
    3. C0-|C-1|-|C+1 |>= LF

    Where: C0 is the main cursor (boost), C-1 is the pre-cursor (pre-shoot), and C+1 is the post-cursor (de-emphasis).

  3. This process is repeated until the downstream component's receiver achieves a BER of < 10-12

Phase 3 (Optional)

During this phase, the Root Port tunes the Endpoint’s transmitter. This process is analogous to Phase 2 but operates in the opposite direction.

After Phase 3 tuning is complete, the Root Port moves to Recovery.RcvrLock, sending EC=2’b00, and the final coefficients or preset agreed upon in Phase 2. The Endpoint moves to Recovery.RcvrLock using the final coefficients or preset agreed upon in Phase 3.

Recommendations for Tuning Link

To improve the BER of the receiver, Intel recommends that you turn on CTLE in triggered mode during Phase 2 Equalization for Endpoints or Phase 3 Equalization for Root Ports.

Use the port pipe_g3_txdeemph[17:0] to transmit the coefficients corresponding to the Gen3 presets. Intel® recommends transmitting Preset P8 coefficients for A10 receiver to recover data successfully. The pipe_g3_txdeemph is used to select the link partner’s transmitter de-emphasis during equalization.

Use the port pipe_g3_rxpresethint[2:0] to turn on CTLE in triggered mode during equalization phases.

Table 197.  CTLE mode for Gen1/Gen2 speeds of Gen3 capable designUse this table to drive the pipe_g3_rxpresethint port and set the CTLE in manual mode when operating at Gen1/Gen2 speeds of a Gen3 capable design.
Gen3 capable design running at Gen1/Gen2 speeds during Supported CTLE - mode Manual. To use CTLE in manual mode
Power up
  • During power up, set pipe_g3_rxpresethint[2:0] = 3’b000
  • You can use the default CTLE 4S AC Gain set by Quartus (or)
  • Set the manual CTLE 4S AC Gain using QSF assignments
Down train to Gen1/Gen2 (directed or not) and subsequent re-entry to Gen3
  • On entry to Gen1/2, set pipe_g3_rxpresethint[2:0] = 3’b000
  • You can use the default CTLE 4S AC Gain set by Quartus (or)
  • Set the manual CTLE 4S AC Gain using QSF assignments
Down train to Gen1/Gen2
  • On entry to Gen1/2, set pipe_g3_rxpresethint[2:0] = 3’b000
  • You can use the default CTLE 4S AC Gain set by Quartus (or)
  • Set the manual CTLE 4S AC Gain using QSF assignments
Note: Intel® does not support use of CTLE in adaptive mode for Gen1/Gen2 speeds. You must use CTLE in manual mode.
Table 198.  CTLE mode for Gen3 speed of Gen3 capable designUse this table to drive the pipe_g3_rxpresethint port and set the CTLE mode to adaptation mode when operating at Gen3 speed for Gen3 capable designs.
Gen3 capable design running at Gen3 speed during Supported CTLE - mode Triggered adaptation. To use CTLE in adaptation mode, Set
1st time entry to Gen3
  • In EQ Phase2/3, after far end TX preset/coefficient requests are completed, set pipe_g3_rxpresethint = 3’b111 and link needs to stay in Recovery for at least 12ms for CTLE adaptation
  • If there is not enough time in EQ phases, delay can be inserted in Recovery.RcvrLock after the EQ
  • After that, pipe_g3_rxpresethint should remain 3’b111 for Gen3 even in Recovery
Redoing EQ in Gen3
  • pipe_g3_rxpresethint should be set to 3’b000 in EQ Phase2/3 entry
  • Follow the same procedure as first time link up to Gen3

Re-entry to Gen3 after down train to Gen1/Gen2 (directed or not)
  • On subsequent entry to Gen3, set pipe_g3_rxpresethint[2:0] = 3’b111 when there is valid data and wait for 12ms in Recovery state for CTLE adaptation
Note:

Intel® recommends that you use CTLE in adaptive mode for Gen3 speed. If you want to use CTLE in manual mode for Gen3 speed, then you must set pipe_g3_rxpresethint[2:0] = 3’b000 and set the CTLE 4S AC gain value

  • You can use the default CTLE 4S AC Gain set by Quartus (or)
  • Set the manual CTLE 4S AC Gain using QSF assignments

Did you find the information on this page useful?

Characters remaining:

Feedback Message