Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

7. Calibration

Transceivers include both analog and digital blocks that require calibration to compensate for process, voltage, and temperature (PVT) variations. Arria 10 transceiver uses hardened Precision Signal Integrity Calibration Engine (PreSICE) to perform calibration routines.

Power-up Calibration and User Recalibration are the main types of calibration.

  • Power-up calibration occurs automatically at device power-up. It runs during device configuration.
  • If you perform dynamic reconfiguration, then you must perform User Recalibration. In this case, you are responsible for enabling the required calibration sequence.
Note: If you are recalibrating your ATX PLL or fPLL, follow the ATX PLL-to-ATX PLL or fPLL-to-ATX PLL spacing guideline as stated in the "Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" chapter.

Arria® 10 devices use CLKUSR for transceiver calibration. To successfully complete the calibration process, the CLKUSR clock must be stable and free running at the start of FPGA configuration. Also, all reference clocks driving transceiver PLLs (ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of FPGA configuration. For more information about CLKUSR pin requirements, refer to the Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines.

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