Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

6.2.2. Writing to the Reconfiguration Interface

Writing to the reconfiguration interface of the Transceiver Native PHY IP core or TX PLL IP core changes the data value at a specific address. All writes to the reconfiguration interface must be read-modify-writes, because two or more features may share the same reconfiguration address. When two or more features share the same reconfiguration address, one feature's data bits are interleaved with another feature's data bits.
Figure 271. Writing to the Reconfiguration Interface
Note: You must check for the internal configuration bus arbitration before performing reconfiguration. Refer to the Arbitration section for more details about requesting access to and returning control of the internal configuration bus from PreSICE.

Did you find the information on this page useful?

Characters remaining:

Feedback Message