Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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8.5.1.4. XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL

Pin planner or Assignment Editor Name

Receiver High Data Rate Mode Equalizer AC Gain Control

Description

Controls the AC gain of the continuous time linear equalizer (CTLE) in high data rate mode and when adaptation is in manual mode (adaptation is disabled).

High data rate mode is enabled by default for data rates up to 25.8 Gbps. In high data rate mode, there is only one CTLE stage and 16 possible AC gain settings. Higher gain setting results in larger AC gain. The default value is set to RADP_CTLE_EQZ_1S_SEL_3 i.e. CTLE AC Gain Setting 3. This QSF assignment only takes effect when one stage CTLE is enabled. If configured in four stage mode, it has no effect on CTLE gain value.

For datarate > 17.4 Gbps, default value is RADP_CTLE_EQZ_1S_SEL_13.

For datarate ≤ 17.4 Gbps, default value is RADP_CTLE_EQZ_1S_SEL_3.

Table 312.  Available Options

Value

Description

RADP_CTLE_EQZ_1S_SEL_<0 to 15>

CTLE AC Gain Setting < 0 to 15>

Assign To

RX serial data pin.

Syntax

set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL <value> -to <rx_serial_data pin name>

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