Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Document Table of Contents Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2 Transceiver Configurations

Figure 63. High BERThis figure shows the rx_enh_highber status signal going high when there are errors on the rx_parallel_data output.
Figure 64.  Block Lock AssertionThis figure shows the assertion on rx_enh_blk_lock signal when the Receiver detects the block delineation.

The following figures show Idle insertion and deletion.