Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.2.4. Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2 Transceiver Configurations

Figure 63. High BERThis figure shows the rx_enh_highber status signal going high when there are errors on the rx_parallel_data output.
Figure 64.  Block Lock AssertionThis figure shows the assertion on rx_enh_blk_lock signal when the Receiver detects the block delineation.

The following figures show Idle insertion and deletion.

Figure 65.  IDLE Word InsertionThis figure shows the insertion of IDLE words in the receiver data stream.
Figure 66.  IDLE Word DeletionThis figure shows the deletion of IDLE words from the receiver data stream.
Figure 67.  OS Word DeletionThis figure shows the deletion of Ordered set word in the receiver data stream.

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