Visible to Intel only — GUID: nik1398706937886
Ixiasoft
Visible to Intel only — GUID: nik1398706937886
Ixiasoft
2.7.5. Native PHY IP Parameter Settings for PIPE
Gen1 PIPE | Gen2 PIPE | Gen3 PIPE | |
---|---|---|---|
Parameter | |||
Message level for rule violations | Error | Error | Error |
Common PMA Options | |||
VCCR_GXB and VCCT_GXB supply voltage for the Transceiver | Gen1: 1_1V, 1_0V, 0_9V | Gen2: 1_1V, 1_0V, 0_9V | Gen3: 1_1V, 1_0V, 0_9V |
Transceiver link type | Gen1: sr,lr | Gen2: sr,lr | Gen3: sr,lr |
Datapath Options | |||
Transceiver configuration rules | Gen1 PIPE | Gen2 PIPE | Gen3 PIPE |
PMA configuration rules | Basic | Basic | Basic |
Transceiver mode | TX / RX Duplex | TX / RX Duplex | TX / RX Duplex |
Number of data channels | Gen1 x1: 1 channel Gen1 x2: 2 channels Gen1 x4: 4 channels Gen1 x8: 8 channels |
Gen2 x1: 1 channel Gen2 x2: 2 channels Gen2 x4: 4 channels Gen2 x8: 8 channels |
Gen3 x1: 1 channel Gen3 x2: 2 channels Gen3 x4: 4 channels Gen3 x8: 8 channels |
Data rate | 2.5 Gbps | 5 Gbps | 5 Gbps40 |
Enable datapath and interface reconfiguration | Optional | Optional | Optional |
Enable simplified data interface | Optional 41 | Optional 41 | Optional 41 |
Provide separate interface for each channel | Optional | Optional | Optional |
Gen1 PIPE | Gen2 PIPE | Gen3 PIPE | |
---|---|---|---|
TX Bonding Options | |||
TX channel bonding mode | Nonbonded (x1) PMA & PCS Bonding |
Nonbonded (x1) PMA & PCS Bonding |
Nonbonded (x1) PMA & PCS Bonding |
PCS TX channel bonding master | Auto 42 | Auto 42 | Auto 42 |
Default PCS TX channel bonding master | Gen1 x1: 0 Gen1 x2: 1 Gen1 x4: 2 Gen1 x8: 4 |
Gen1 x1: 0 Gen1 x2: 1 Gen1 x4: 2 Gen1 x8: 4 |
Gen1 x1: 0 Gen1 x2: 1 Gen1 x4: 2 Gen1 x8: 4 |
TX PLL Options | |||
TX local clock division factor | 1 | 1 | 1 |
Number of TX PLL clock inputs per channel | 1 | 1 | Gen3 x1: 2 All other modes: 1 |
Initial TX PLL clock input selection | 0 | 0 | Gen1 / Gen2 clock connection should be used for Initial clock input selection in Gen3x1 All other modes: 0 |
TX PMA Optional Ports | |||
Enable tx_analog_reset_ack port | Optional | Optional | Optional |
Enable tx_pma_clkout port | Optional | Optional | Optional |
Enable tx_pma_div_clkout port | Optional | Optional | Optional |
tx_pma_div_clkout division factor | Optional | Optional | Optional |
Enable tx_pma_elecidle port | Off | Off | Off |
Enable |