Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.7.5. Native PHY IP Parameter Settings for PIPE

Table 185.  Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 ModesThis section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Gen1 PIPE Gen2 PIPE Gen3 PIPE
Parameter
Message level for rule violations Error Error Error
Common PMA Options
VCCR_GXB and VCCT_GXB supply voltage for the Transceiver Gen1: 1_1V, 1_0V, 0_9V Gen2: 1_1V, 1_0V, 0_9V Gen3: 1_1V, 1_0V, 0_9V
Transceiver link type Gen1: sr,lr Gen2: sr,lr Gen3: sr,lr
Datapath Options
Transceiver configuration rules Gen1 PIPE Gen2 PIPE Gen3 PIPE
PMA configuration rules Basic Basic Basic
Transceiver mode TX / RX Duplex TX / RX Duplex TX / RX Duplex
Number of data channels

Gen1 x1: 1 channel

Gen1 x2: 2 channels

Gen1 x4: 4 channels

Gen1 x8: 8 channels

Gen2 x1: 1 channel

Gen2 x2: 2 channels

Gen2 x4: 4 channels

Gen2 x8: 8 channels

Gen3 x1: 1 channel

Gen3 x2: 2 channels

Gen3 x4: 4 channels

Gen3 x8: 8 channels

Data rate 2.5 Gbps 5 Gbps 5 Gbps40
Enable datapath and interface reconfiguration Optional Optional Optional
Enable simplified data interface Optional 41 Optional 41 Optional 41
Provide separate interface for each channel Optional Optional Optional
Table 186.  Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMAThis section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Gen1 PIPE Gen2 PIPE Gen3 PIPE
TX Bonding Options
TX channel bonding mode

Nonbonded (x1)

PMA & PCS Bonding

Nonbonded (x1)

PMA & PCS Bonding

Nonbonded (x1)

PMA & PCS Bonding

PCS TX channel bonding master Auto 42 Auto 42 Auto 42
Default PCS TX channel bonding master

Gen1 x1: 0

Gen1 x2: 1

Gen1 x4: 2

Gen1 x8: 4

Gen1 x1: 0

Gen1 x2: 1

Gen1 x4: 2

Gen1 x8: 4

Gen1 x1: 0

Gen1 x2: 1

Gen1 x4: 2

Gen1 x8: 4

TX PLL Options
TX local clock division factor 1 1 1
Number of TX PLL clock inputs per channel 1 1 Gen3 x1: 2

All other modes: 1

Initial TX PLL clock input selection 0 0 Gen1 / Gen2 clock connection should be used for Initial clock input selection in Gen3x1

All other modes: 0

TX PMA Optional Ports
Enable tx_analog_reset_ack port Optional Optional Optional
Enable tx_pma_clkout port Optional Optional Optional
Enable tx_pma_div_clkout port Optional Optional Optional
tx_pma_div_clkout division factor Optional Optional Optional
Enable tx_pma_elecidle port Off Off Off
Enable tx_pma_qpipullup port (QPI) Off Off Off
Enable tx_pma_qpipulldn port (QPI) Off Off Off
Enable tx_pma_txdetectrx port (QPI) Off Off Off
Enable tx_pma_rxfound port (QPI) Off Off Off
Enable rx_seriallpbken port Off Off Off
Table 187.  Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - RX PMAThis section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Gen1 PIPE Gen2 PIPE Gen3 PIPE
RX CDR Options
Number of CDR reference clocks 1 1 1
Selected CDR reference clock 0 0 0
Selected CDR reference clock frequency 100, 125 MHz 100, 125 MHz 100, 125 MHz
PPM detector threshold 1000 1000 1000
Equalization
CTLE adaptation mode
Note: Triggered adaptation mode is used only for PCIe* Gen3.
Manual / Triggered Manual / Triggered Manual / Triggered
DFE adaptation mode Disabled Disabled Disabled
Number of fixed dfe taps NA NA NA
RX PMA Optional Ports
Enable rx_analog_reset_ack port Optional Optional Optional
Enable rx_pma_clkout port Optional Optional Optional
Enable rx_pma_div_clkout port Optional Optional Optional
rx_pma_div_clkout division factor Optional Optional Optional
Enable rx_pma_clkslip port Optional Optional Optional
Enable rx_pma_qpipulldn port (QPI) Off Off Off
Enable rx_is_lockedtodata port Optional Optional Optional
Enable rx_is_lockedtoref port Optional Optional Optional
Enable rx_set_locktodata and rx_set_locktoref ports Optional Optional Optional
Enable rx_seriallpbken port Optional Optional Optional
Enable PRBS Verifier Control and Status ports Optional Optional Optional
Table 188.  Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - Standard PCSThis section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE
Standard PCS configurations
Standard PCS / PMA interface width 10 10 1043
FPGA Fabric / Standard TX PCS interface width 8, 16 16 32
FPGA Fabric / Standard RX PCS interface width 8, 16 16 32
Enable Standard PCS low latency mode Off Off Off
Standard PCS FIFO
TX FIFO mode low_latency low_latency low_latency
RX FIFO mode low_latency low_latency low_latency
Enable tx_std_pcfifo_full port Optional Optional Optional
Enable tx_std_pcfifo_empty port Optional Optional Optional
Enable rx_std_pcfifo_full port Optional Optional Optional
Enable rx_std_pcfifo_empty port Optional Optional Optional
Byte Serializer and Deserializer
TX byte serializer mode Disabled, Serialize x2 Serialize x2 Serialize x4
RX byte deserializer mode Disabled, Serialize x2 Serialize x2 Deserialize x4
8B/10B Encoder and Decoder
Enable TX 8B/10B encoder Enabled Enabled Enabled
Enable TX 8B/10B disparity control Enabled Enabled Enabled
Enable RX 8B/10B decoder Enabled Enabled Enabled
Rate Match FIFO
Rate Match FIFO mode PIPE, PIPE 0ppm PIPE, PIPE 0ppm PIPE, PIPE 0ppm
RX rate match insert / delete -ve pattern (hex) 0x0002f17c (K28.5/K28.0/) 0x0002f17c (K28.5/K28.0/) 0x0002f17c (K28.5/K28.0/)
RX rate match insert / delete +ve pattern (hex) 0x000d0e83 (K28.5/K28.0/) 0x000d0e83 (K28.5/K28.0/) 0x000d0e83 (K28.5/K28.0/)
Enable rx_std_rmfifo_full port Optional Optional Optional
Enable rx_std_rmfifo_empty port Optional Optional Optional
PCI Express* Gen 3 rate match FIFO mode Bypass Bypass 600
Word Aligner and Bit Slip
Enable TX bit slip Off Off Off
Enable tx_std_bitslipboundarysel port Optional Optional Optional
RX word aligner mode Synchronous State Machine Synchronous State Machine Synchronous State Machine
RX word aligner pattern length 10 10 10
RX word aligner pattern (hex) 0x0000 00000000017c (/K28.5/) 0x0000 00000000017c (/K28.5/) 0x0000 00000000017c(/K28.5/)
Number of word alignment patterns to achieve sync 3 3 3
Number of invalid data words to lose sync 16 16 16
Number of valid data words to decrement error count 15 15 15
Enable rx_std_wa_patternalign port Optional Optional Optional
Enable rx_std_wa_a1a2size port Off Off Off
Enable rx_std_bitslipboundarysel port Optional Optional Optional
Enable rx_bitslip port Off Off Off
Bit Reversal and Polarity Inversion
Enable TX bit reversal Off Off Off
Enable TX byte reversal Off Off Off
Enable TX polarity inversion Off Off Off
Enable tx_polinv port Off Off Off
Enable RX bit reversal Off Off Off
Enable rx_std_bitrev_ena port Off Off Off
Enable RX byte reversal Off Off Off
Enable rx_std_byterev_ena port Off Off Off
Enable RX polarity inversion Off Off Off
Enable rx_polinv port Off Off Off
Enable rx_std_signaldetect port Optional Optional Optional
PCIe Ports
Enable PCIe dynamic datarate switch ports Off Enabled Enabled
Enable PCIe pipe_hclk_in and pipe_hclk_out ports Enabled Enabled Enabled
Enable PCIe Gen3 analog control ports Off Off Enabled
Enable PCIe electrical idle control and status ports Enabled Enabled Enabled
Enable PCIe pipe_rx_polarity port Enabled Enabled Enabled
Dynamic reconfiguration
Enable dynamic reconfiguration Disabled Disabled Disabled
Note: The signals in the left-most column are automatically mapped to a subset of a 128-bit tx_parallel_data word when the Simplified Interface is enabled.
40

The PIPE is configured in Gen1/Gen2 during Power Up. Gen3 PCS is configured for 8 Gbps.

41 Refer to Native PHY IP Ports for PIPE for bit settings when simplified data interface is enabled.
42 Setting this parameter is placement-dependent. In AUTO mode, the Native PHY IP Parameter Editor selects the middle-most channel of the configuration as the default PCS TX channel bonding master. You must ensure that this selected channel is physically placed as Ch1 or Ch4 of the transceiver bank. Else, use the manual selection for the PCS TX channel bonding master to select a channel that can be physically placed as Ch1 or Ch4 of the transceiver bank. Refer to section How to place channels for PIPE configurations for more details.
43 The PIPE is configured in Gen1/Gen2 during Power Up. Gen3 PCS is configured for PCS/PMA width of 32.

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