Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents

8.11. Analog Parameter Settings Revision History

Document Version Changes
2018.10.16 Made the following changes:
  • For PRESERVE_UNUSED_XCVR_CHANNEL, clarified that an example of <pin_name> is U34, not PIN_U34.
  • In XCVR_A10_RX_EQ_DC_GAIN_TRIM, updated the Receiver High Gain Mode Equalizer DC Gain Control value descriptions from 6, 13, 20, 27 to 7, 14, 21 and 28 to match the Assignment Editor GUI.
2017.11.06 Made the following changes:
  • Changed all default values of RADP_VGA_SEL to 4 in the "XCVR_A10_RX_ADP_VGA_SEL" section.
2016.10.31 Made the following changes:
  • Added the Value in Assignment Editor column to the table in the "XCVR_A10_RX_ONE_STAGE_ENABLE" section.
  • Added a note to the "XCVR_A10_TX_SLEW_RATE_CTRL" section.
2016.05.02 Made the following changes:
  • Updated that "DFE continuous mode" is not supported any more. DFE is supported in three modes-Disabled, Manual, Adaptation Enabled.
  • Changed the "Arria 10 Register Map” for available DFE