Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents

7.3. Power-up Calibration

After the device is powered up and programmed, PreSICE automatically initiates the calibration process. The calibration process may continue during device programming. The time required after device power-up to complete the calibration process can vary by device. The total time taken can extend into the user-mode. The cal_busy signals deassert to indicate the completion of the calibration process. You must ensure that the transceiver reset sequence in your design waits for the calibration to complete before resetting the transceiver PLL and the transceiver channel.

The PreSICE may still control the internal configuration bus even after power-up calibration is complete. You can request access when needed. If a system has an fPLL, an ATX PLL, and channels, the fPLL cal_busy signal goes low first. The ATX PLL cal_busy signal goes low after the channels’ tx_cal_busy and rx_cal_busy signals. Intel recommends that you wait until all *_cal_busy signals are low before requesting any access.

All power-up calibration starts from Vreg calibration for all banks and channels.

PCIe* link does not allow user recalibration, so you must perform power-up calibration.

Furthermore, power-up calibration for channels configured with the PCIe* protocol require a reference clock. Without the presence of a reference clock, power-up calibration does not start but waits indefinitely, so supply a reference clock to the PCIe* refclk pin for the power-up calibration process.

Figure 284. Power-up Calibration Sequence for Non- PCIe* Hard IP (HIP) ChannelsFor applications not using PCIe* Hard IP, the power-up calibration starts from Vreg calibration for all banks and channels. Then, PreSICE calibration is done in the sequence as shown in the following figure.
For applications using both PCIe* Hard IP and non- PCIe* channels, the power-up calibration sequence is:
  1. Vreg calibration for all banks and channels.
  2. Wait for PCIe* reference clock toggle.
  3. PCIe* Hard IP 0 calibration (if used).
  4. PCIe* Hard IP 1 calibration (if used).
  5. Calibration of all non- PCIe* Hard IP channels in calibration sequence.
Figure 285. Power-up Calibration Sequence for PCIe* Hard IP and non- PCIe* Channels

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