Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Public
Document Table of Contents

1. Arria® 10 Transceiver PHY Overview

Updated for:
Intel® Quartus® Prime Design Suite 21.1
This user guide provides details about the Arria® 10 transceiver physical (PHY) layer architecture, PLLs, clock networks, and transceiver PHY IP. It also provides protocol specific implementation details and describes features such as transceiver reset and dynamic reconfiguration of transceiver channels and PLLs.

Intel® Arria® 10 FPGAs offer up to 96 GX transceiver channels with integrated advanced high speed analog signal conditioning and clock data recovery techniques for chip-to-chip, chip-to-module, and backplane applications.

The Arria® 10 GX and SX devices have GX transceiver channels that can support data rates up to 17.4 Gbps for chip-to-chip applications and 12.5 Gbps for backplane applications.

The Arria® 10 GT device has up to 6 GT transceiver channels, that can support data rates up to 25.8 Gbps for short reach chip-to-chip and chip-to-module applications. Additionally, the GT devices have GX transceiver channels that can support data rates up to 17.4 Gbps for chip-to-chip and 12.5 Gbps for backplane applications. If all 6 GT channels are used in GT mode, then the GT device also has up to 54 GX transceiver channels.

The Arria® 10 transceivers support reduced power modes with data rates up to 11.3 Gbps (chip-to-chip) for critical power sensitive designs. In GX devices that have transceivers on both sides of the device, each side can be operated independently in standard and reduced power modes. You can achieve transmit and receive data rates below 1.0 Gbps with oversampling.

Table 1.  Data Rates Supported by GX Transceiver Channel Type
Device Variant Standard Power Mode 1 , 2