2.7.4. How to Implement PCI Express* (PIPE) in Arria 10 Transceivers
You must be familiar with the Standard PCS architecture, Gen3 PCS architecture, PLL architecture, and the reset controller before implementing the PCI Express protocol.
- Go to the IP Catalog and select the Arria 10 Transceiver Native PHY IP Core. Refer to Select and Instantiate the PHY IP Core for more details.
- Select Gen1/Gen2/Gen3 PIPE from the Arria 10 Transceiver configuration rules list, located under Datapath Options.
- Use the parameter values in the tables in Transceiver Native PHY IP Parameters for PCI Express Transceiver Configurations Rules as a starting point. Alternatively, you can use Arria 10 Transceiver Native PHY Presets . You can then modify the settings to meet your specific requirements.
- Click Finish to generate the Native PHY IP (this is your RTL file).
- Instantiate and configure your PLL.
- Create a transceiver reset controller. You can use your own reset controller or use the Transceiver PHY Reset Controller.
- Connect the Native PHY IP to the PLL IP core and the reset controller. Use the information in Transceiver Native PHY IP Ports for PCI Express Transceiver Configuration Rules to connect the ports.
- Simulate your design to verify its functionality.
Intel recommends that you not reset the PLL and channels (TX and RX) when using the PIPE mode of Native PHY. This is to avoid resetting the Auto Speed Negotiation (ASN) block in the PCS.
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