184.108.40.206. Implementing Single Channel x1 Non-Bonded Configuration
For a single channel design, a PLL is used to provide the clock to a transceiver channel.
To implement this configuration, instantiate a PLL IP core and a PHY IP core and connect them together as shown in the above figure.
Steps to implement a Single Channel x1 Non-Bonded Configuration
- Instantiate the PLL IP core (ATX PLL, fPLL, or CMU PLL) you want to use in your design.
- Configure the PLL IP core using the IP Parameter Editor.
- For ATX PLL IP core, do not include the Master CGB.
- For fPLL IP core, set the PLL feedback operation mode to direct.
- For CMU PLL IP core, specify the reference clock and the data rate. No special configuration rule is required.
- Configure the Native PHY IP core using the IP Parameter Editor .
- Set the Native PHY IP Core TX Channel bonding mode to Non Bonded .
- Connect the PLL IP core to the Native PHY IP core. Connect the tx_serial_clk output port of the PLL to IP to the corresponding tx_serial_clk0 input port of the Native PHY IP core. This port represents the input to the local CGB of the channel. The tx_serial_clk for the PLL represents the high speed serial clock generated by the PLL.
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