18.104.22.168.8. PCIe* Reverse Parallel Loopback
PCIe reverse parallel loopback is only available in a PCIe functional configuration for Gen1, Gen2, and Gen3 data rates. The received serial data passes through the receiver CDR, deserializer, word aligner, and rate matching FIFO buffer. The data is then looped back to the transmitter serializer and transmitted out through the transmitter buffer. The received data is also available to the FPGA fabric through the rx_parallel_data port. This loopback mode is based on PCIe specification 2.0. Arria 10 devices provide an input signal pipe_tx_detectrx_loopback to enable this loopback mode.
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