Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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6.13. Ports and Parameters

The reconfiguration interface is integrated in the Native PHY instance and the TX PLL instances. Instantiate the Native PHY and the TX PLL IP cores in Qsys by clicking Tools > IP Catalog. You can define parameters for IP cores by using the IP core-specific parameter editor. To expose the reconfiguration interface ports, select the Enable dynamic reconfiguration option when parameterizing the IP core.

You can share the reconfiguration interface among all the channels by turning on Share reconfiguration interface when parameterizing the IP core. When this option is enabled, the IP core presents a single reconfiguration interface for dynamic reconfiguration of all channels. Address bits [9:0] provide the register address in the reconfiguration space of the selected channel. The remaining address bits of the reconfiguration address specify the selected logical channel. For example, if there are four channels in the Native PHY IP instance, reconfig_address[9:0] specifies the address and reconfig_address[11:10] are binary encoded to specify the four channels. For example, 2'b01 in reconfig_address[11:10] specifies logical channel 1.

The following figure shows the signals available when the Native PHY IP core is configured for four channels and the Share reconfiguration interface option is enabled.

Figure 278. Signals Available with Shared Native PHY Reconfiguration Interface
Table 280.  Reconfiguration Interface Ports with Shared Native PHY Reconfiguration InterfaceThe reconfiguration interface ports when Share reconfiguration interface is enabled. <N> represents the number of channels.
Port Name Direction Clock Domain Description
reconfig_clk Input N/A Avalon® clock. The clock frequency is 100-125 MHz.
reconfig_reset Input reconfig_clk Resets the Avalon® interface. Asynchronous to assertion and synchronous to deassertion.
reconfig_write Input reconfig_clk Write enable signal. Signal is active high.
reconfig_read Input reconfig_clk Read enable signal. Signal is active high.
reconfig_address[log2<N>+9:0] Input reconfig_clk Address bus. The lower 10 bits specify address and the upper bits specify the channel.
reconfig_writedata[31:0] Input reconfig_clk A 32-bit data write bus. Data to be written into the address indicated by reconfig_address.
reconfig_readdata[31:0] Output reconfig_clk A 32-bit data read bus. Valid data is placed on this bus after a read operation. Signal is valid after reconfig_waitrequest goes high and then low.
reconfig_waitrequest Output reconfig_clk A one-bit signal that indicates the Avalon® interface is busy. Keep the Avalon® command asserted until the interface is ready to proceed with the read/write transfer. The behavior of this signal depends on whether the feature Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE is enabled or not. For more details, refer to the Arbitration section.

When Share reconfiguration interface is off, the Native PHY IP core provides an independent reconfiguration interface for each channel. For example, when a reconfiguration interface is not shared for a four-channel Native PHY IP instance, reconfig_address[9:0] corresponds to the reconfiguration address bus of logical channel 0, reconfig_address[19:10] correspond to the reconfiguration address bus of logical channel 1, reconfig_address[29:20] corresponds to the reconfiguration address bus of logical channel 2, and reconfig_address[39:30] correspond to the reconfiguration address bus of logical channel 3.

The following figure shows the signals available when the Native PHY is configured for four channels and the Share reconfiguration interface option is not enabled.

Figure 279. Signals Available with Independent Native PHY Reconfiguration Interfaces
Table 281.  Reconfiguration Interface Ports with Independent Native PHY Reconfiguration InterfacesThe reconfiguration interface ports when Share reconfiguration interface is disabled. <N> represents the number of channels.
Port Name Direction Clock Domain Description
reconfig_clk[N-1:0] Input N/A Avalon® clock for each channel. The clock frequency is 100-125 MHz.
reconfig_reset[N-1:0] Input reconfig_clk Resets the Avalon® interface for each channel. Asynchronous to assertion and synchronous to deassertion.
reconfig_write[N-1:0] Input reconfig_clk Write enable signal for each channel. Signal is active high.
reconfig_read[N-1:0] Input reconfig_clk Read enable signal for each channel. Signal is active high.
reconfig_address[N*10-1:0] Input reconfig_clk A 10-bit address bus for each channel.
reconfig_writedata[N*32-1:0] Input reconfig_clk A 32-bit data write bus for each channel. Data to be written into the address indicated by the corresponding address field in reconfig_address.
reconfig_readdata[N*32-1:0] Output reconfig_clk A 32-bit data read bus for each channel. Valid data is placed on this bus after a read operation. Signal is valid after waitrequest goes high and then low.
reconfig_waitrequest[N-1:0] Output reconfig_clk A one-bit signal for each channel that indicates the Avalon® interface is busy. Keep the Avalon® command asserted until the interface is ready to proceed with the read/write transfer. The behavior of this signal depends on whether the feature Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE is enabled or not. For more details, refer to the Arbitration section.
Table 282.   Avalon® Interface ParametersThe following parameters are available in the Dynamic Reconfiguration tab of the Transceiver Native PHY and TX PLL parameter editors.
Note: The Native PHY and the PLL IP Parameter Editors give an error or warning message if any of the parameter selections violate the legality checks.
Parameter Value Description
Enable dynamic reconfiguration On / Off Available in Native PHY and TX PLL IP parameter editors. Enables the reconfiguration interface. Off by default. The reconfiguration interface is exposed when this option is enabled.
Share reconfiguration interface On / Off Available in Native PHY IP parameter editor only. Enables you to use a single reconfiguration interface to control all channels. Off by default. If enabled, the uppermost bits of reconfig_address identifies the active channel. The lower 10 bits specify the reconfiguration address. Binary encoding is used to identify the active channel (available only for Transceiver Native PHY). Enable this option if the Native PHY is configured with more than one channel.
Enable Native PHY Debug Master Endpoint On / Off Available in Native PHY and TX PLL IP parameter editors. When enabled, the Native PHY Debug Master Endpoint (NPDME) is instantiated and has access to the Avalon® memory-mapped interface of the Native PHY. You can access certain test and debug functions using System Console with the NPDME. Refer to the Embedded Debug Features section for more details about NPDME.
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE On / Off When enabled, reconfig_waitrequest do not indicate the status of Avalon® memory-mapped interface arbitration with PreSICE. The Avalon® memory-mapped interface arbitration status is reflected in a soft status register bit. This feature requires that the Enable control and status registers feature under Optional Reconfiguration Logic be enabled. Refer to Arbitration for more details on this feature. Refer to the Calibration chapter for more details about calibration.
Enable capability registers On / Off Available in Native PHY and TX PLL IP parameter editors. Enables capability registers. These registers provide high-level information about the transceiver channel's /PLL's configuration.
Set user-defined IP identifier User-specified Available in Native PHY and TX PLL IP parameter editors. Sets a user-defined numeric identifier that can be read from the user_identifier offset when the capability registers are enabled.
Enable control and status registers On / Off Available in Native PHY and TX PLL IP parameter editors. Enables soft registers for reading status signals and writing control signals on the PHY/PLL interface through the NPDME or reconfiguration interface.
Enable PRBS soft accumulators On / Off Available in Native PHY IP parameter editor only. Enables soft logic to perform PRBS bit and error accumulation when using the hard PRBS generator and checker.
Configuration file prefix User-specified Available in Native PHY and TX PLL IP parameter editors. Specifies the file prefix used for generating configuration files. Use a unique prefix for configuration files for each variant of the Native PHY and PLL.
Generate SystemVerilog package file On / Off Available in Native PHY and TX PLL IP parameter editors. Creates a SystemVerilog package file that contains the current configuration data values for all reconfiguration addresses. Disabled by default.
Generate C header file On / Off Available in Native PHY and TX PLL IP parameter editors. Creates a C header file that contains the current configuration data values for all reconfiguration addresses. Disabled by default.
Generate MIF (Memory Initialize File) On / Off Available in Native PHY and TX PLL IP parameter editors. Creates a MIF file that contains the current configuration data values for all reconfiguration addresses. Disabled by default.
Include PMA analog settings in the configuration files On / Off Available in Native PHY IP parameter editor only. When enabled, the IP allows you to configure the analog settings for the PMA. These settings are included in your generated configuration files.
Note: Even with this option enabled in the Native PHY IP Parameter Editor, you must still specify QSF assignments for your analog settings when compiling your static design. The analog settings selected in the Native PHY IP Parameter Editor are used only to include these settings and their dependent settings in the selected configuration files. For details about QSF assignments for the analog settings, refer to the Analog Parameter Settings chapter.
Enable multiple reconfiguration profiles On / Off Available in Native PHY and ATX PLL IP parameter editors only. Use the Parameter Editor to store multiple configurations. The parameter settings for each profile are tabulated in the Parameter Editor.
Enable embedded reconfiguration streamer On / Off Available in Native PHY and ATX PLL IP parameter editors only. Embeds the reconfiguration streamer into the Native PHY/ATX PLL IP cores and automates the dynamic reconfiguration process between multiple predefined configuration profiles.
Generate reduced reconfiguration files On / Off Available in Native PHY and ATX PLLIP parameter editors only. Enables the Native PHY and ATX PLL IP cores to generate reconfiguration files that contain only the attributes that differ between multiple profiles.
Number of reconfiguration profiles 1 to 8 Available in Native PHY and ATX PLL IP parameter editors only. Specifies the number of reconfiguration profiles to support when multiple reconfiguration profiles are enabled.
Selected reconfiguration profile 0 to 7 Available in Native PHY and ATX PLL IP parameter editors only. Selects which reconfiguration profile to store when you click Store profile.
Store configuration to selected profile N/A Available in Native PHY and ATX PLL IP parameter editors only. Stores the current Native PHY and ATX PLL parameter settings to the profile specified by the Selected reconfiguration profile parameter.
Load configuration from selected profile N/A Available in Native PHY and ATX PLL IP parameter editors only. Loads the current Native PHY/ATX PLL IP with parameter settings from the stored profile specified by the Selected reconfiguration profile parameter.
Clear selected profile N/A Available in Native PHY and ATX PLL IP parameter editors only. Clears the stored Native PHY/ATX PLL IP parameter settings for the profile specified by the Selected reconfiguration profile parameter. An empty profile defaults to the current parameter settings of the Native PHY/ATX PLL. In other words, an empty profile reflects the Native PHY/ATX PLL current parameter settings.
Clear all profiles N/A Available in Native PHY and ATX PLL IP parameter editors only. Clears the Native PHY/ATX PLL IP parameter settings for all the profiles.
Refresh selected_profile N/A Available in Native PHY and ATX PLL IP parameter editors only. Equivalent to clicking the Load configuration from selected profile and Store configuration to selected profile buttons in sequence. This operation loads the parameter settings from stored profile specified by the Selected reconfiguration profile parameter and then stores the parameters back to the profile.
Table 283.  Analog PMA Settings (Optional) for Dynamic ReconfigurationThe following parameters are available in the Analog PMA Settings (Optional) tab of the Transceiver Native PHY parameter editor. Refer to Changing PMA Analog Parameters for more details. Refer to the Analog Parameter Settings chapter for details about using the QSF assignments.
Parameter Value Description
TX Analog PMA Settings
Analog Mode (Load Intel-recommended Default settings) cei_11100_lr to xfp_9950 Selects the analog protocol mode to pre-select the TX pin swing settings (VOD, Pre-emphasis, and Slew Rate). After loading the pre-selected values in the Parameter Editor, if one or more of the individual TX pin swing settings need to be changed, then enable the option to override the Intel-recommended defaults to individually modify the settings. For details about QSF assignments for the analog settings, refer to the Analog Parameter Settings chapter.
Override Intel-recommended Analog Mode Default settings On / Off Enables the option to override the Intel-recommended settings for the selected TX Analog Mode for one or more TX analog parameters.
Output Swing Level (VOD) 0-31 Selects the transmitter programmable output differential voltage swing.
Pre-Emphasis First Pre-Tap Polarity Fir_pre_1t_neg, Fir_pre_1t_pos Selects the polarity of the first pre-tap for pre-emphasis.
Pre-Emphasis First Pre-Tap Magnitude 0-16 Selects the magnitude of the first pre-tap for pre-emphasis.
Pre-Emphasis Second Pre-Tap Polarity Fir_pre_2t_neg, Fir_pre_2t_pos Selects the polarity of the second pre-tap for pre-emphasis.
Pre-Emphasis Second Pre-Tap Magnitude 0-7 Selects the magnitude of the second pre-tap for pre-emphasis.
Pre-Emphasis First Post-Tap Polarity Fir_post_1t_neg, Fir_post_1t_pos Selects the polarity of the first post-tap for pre-emphasis.
Pre-Emphasis First Post-Tap Magnitude 0-25 Selects the magnitude of the first post-tap for pre-emphasis.
Pre-Emphasis Second Post-Tap Polarity Fir_post_2t_neg, Fir_post_2t_pos Selects the polarity of the second post-tap for pre-emphasis.
Pre-Emphasis Second Post-Tap Magnitude 0-12 Selects the magnitude of the second post-tap for pre-emphasis.
Slew Rate Control slew_r0 to slew_r5 Selects the slew rate of the TX output signal. Valid values span from slowest to the fastest rate.
High-Speed Compensation Enable / Disable Enables the power-distribution network (PDN) induced inter-symbol interference (ISI) compensation in the TX driver. When enabled, it reduces the PDN induced ISI jitter, but increases the power consumption.
On-Chip termination r_r1, r_r2 Selects the on-chip TX differential termination.
RX Analog PMA settings
Override Intel-recommended Default settings On / Off Enables the option to override the Intel-recommended settings for one or more RX analog parameters. For details about QSF assignments for the analog settings, refer to the Analog Parameter Settings chapter.
CTLE (Continuous Time Linear Equalizer) mode non_s1_mode, s1_mode Selects between the RX high gain mode (non_s1_mode) or RX high data rate mode (s1_mode) for the Continuous Time Linear Equalizer (CTLE).
DC gain control of high gain mode CTLE no_dc_gain to stg4_gain7 Selects the DC gain of the Continuous Time Linear Equalizer (CTLE) in high gain mode
AC Gain Control of High Gain Mode CTLE radp_ctle_acgain_4s_0 to radp_ctle_acgain_4s_28 Selects the AC gain of the Continuous Time Linear Equalizer (CTLE) in high gain mode when CTLE is in manual mode
AC Gain Control of High Data Rate Mode CTLE radp_ctle_eqz_1s_sel_0 to radp_ctle_eqz_1s_sel_15 Selects the AC gain of the Continuous Time Linear Equalizer (CTLE) in high data rate mode when CTLE is in manual mode
Variable Gain Amplifier (VGA) Voltage Swing Select radp_vga_sel_0 to radp_vga_sel_7 Selects the Variable Gain Amplifier (VGA) output voltage swing when both the CTLE and DFE blocks are in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 1 Coefficient radp_dfe_fxtap1_0 to radp_dfe_fxtap1_127 Selects the coefficient of the fixed tap 1 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 2 Coefficient radp_dfe_fxtap2_0 to radp_dfe_fxtap2_127 Selects the coefficient of the fixed tap 2 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 3 Coefficient radp_dfe_fxtap3_0 to radp_dfe_fxtap3_127 Selects the coefficient of the fixed tap 3 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 4 Coefficient radp_dfe_fxtap4_0 to radp_dfe_fxtap4_63 Selects the coefficient of the fixed tap 4 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 5 Coefficient radp_dfe_fxtap5_0 to radp_dfe_fxtap5_63 Selects the coefficient of the fixed tap 5 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 6 Coefficient radp_dfe_fxtap6_0 to radp_dfe_fxtap6_31 Selects the coefficient of the fixed tap 6 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 7 Coefficient radp_dfe_fxtap7_0 to radp_dfe_fxtap7_31 Selects the coefficient of the fixed tap 7 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 8 Coefficient radp_dfe_fxtap8_0 to radp_dfe_fxtap8_31 Selects the coefficient of the fixed tap 8 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 9 Coefficient radp_dfe_fxtap9_0 to radp_dfe_fxtap9_31 Selects the coefficient of the fixed tap 9 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 10 Coefficient radp_dfe_fxtap10_0 to radp_dfe_fxtap10_31 Selects the coefficient of the fixed tap 10 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 11 Coefficient radp_dfe_fxtap11_0 to radp_dfe_fxtap11_31 Selects the coefficient of the fixed tap 11 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
On-Chip termination r_ext0, r_r1, r_r2 Selects the on-chip RX differential termination.

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