Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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6.15.2.2. Control and Status Registers

Control and status registers are optional registers that memory-map some of the status outputs from and control inputs to the Native PHY and PLL.

The following control and status registers are available for the Native PHY IP core.

Table 286.  Control Registers for the Native PHY IP Core
Address Type Register Description
0x2E0[0] RW set_rx_locktodata Asserts the set_rx_locktodata signal to the receiver. 1'b1 sets the NPDME set_rx_locktodata register. See override_set_rx_locktodata.
0x2E0[1] RW set_rx_locktoref Asserts the set_rx_locktoref signal to the receiver. 1'b1 sets the NPDME set_rx_locktoref register. See override_set_rx_locktoref row below.
0x2E0[2] RW override_set_rx_locktodata Selects whether the receiver listens to the NPDME set_rx_locktodata register or the rx_set_locktodata port. 1'b1 indicates that the receiver listens to the NPDME set_rx_locktodata register.
0x2E0[3] RW override_set_rx_locktoref Selects whether the receiver is listens to the NPDME set_rx_locktoref register or the rx_set_locktoref port. 1'b1 indicates that the receiver listens to the NPDME set_rx_locktoref register.
0x2E1[0] RW rx_seriallpbken Enables the rx_seriallopbken feature in the transceiver. 1’b1 enables reverse serial loopback.
0x2E2[0] RW rx_analogreset Drives rx_analogreset when the override is set.
0x2E2[1] RW rx_digitalreset Drives rx_digitalreset when the override is set.
0x2E2[2] RW tx_analogreset Drives tx_analogreset when the override is set.
0x2E2[3] RW tx_digitalreset Drives tx_digitalreset when the override is set.
0x2E2[4] RW override_rx_analogreset Selects whether the receiver listens to the NPDME rx_analogreset register or the rx_analogreset port. 1'b1 indicates the receiver listens to the NPDME rx_analogreset register.
0x2E2[5] RW override_rx_digitalreset Selects whether the receiver listens to the NPDME rx_digitalreset register or the rx_digitalreset port. 1'b1 indicates the receiver listens to the NPDME rx_digitalreset register.
0x2E2[6] RW override_tx_analogreset Selects whether the receiver listens to the NPDME tx_analogreset register or the tx_analogreset port. 1'b1 indicates the receiver listens to the NPDME tx_analogreset register.
0x2E2[7] RW override_tx_digitalreset Selects whether the receiver listens to the NPDME tx_digitalreset register or the tx_digitalreset port. 1'b1 indicates the receiver listens to the NPDME tx_digitalreset register.
Table 287.  Status Registers for the Native PHY IP Core
Address Type Register Description
0x280[0] RO rx_is_lockedtodata Shows the status of the current channel’s rx_is_lockedtodata signal. 1’b1 indicates the receiver is locked to the incoming data.
0x280[1] RO rx_is_lockedtoref Shows the status of the current channel’s rx_is_lockedtoref signal. 1’b1 indicates the receiver is locked to the reference clock.
0x281[0] RO tx_cal_busy Shows the status of the transmitter calibration status. 1’b1 indicates the transmitter calibration is in progress.
0x281[1] RO rx_cal_busy Shows the status of the receiver calibration status. 1’b1 indicates the receiver calibration is in progress.
0x281[2] RO avmm_busy Shows the status of the internal configuration bus arbitration. 1’b1 indicates PreSICE has control of the internal configuration bus. 1'b0 indicates the user has control of the internal configuration bus. Refer to the Arbitration section for more details. For more details about calibration registers and performing user recalibration, refer to the Calibration chapter.

The following control and status registers are available for the PLL IP cores.

Table 288.  Control Registers for the PLL IP Cores
Address Type Register Description
0x2E0[0] RW pll_powerdown Drives the PLL powerdown when the Override is set.
0x2E0[1] RW override_pll_powerdown Selects whether the receiver listens to the NPDME pll_powerdown register or the pll_powerdown port. 1’b1 indicates the receiver listens to the NPDME pll_powerdown.
Table 289.  Status Registers for the PLL IP Cores
Address Type Register Description
0x280[0] RO pll_locked Indicates if the PLL is locked. 1'b1 indicates the PLL is locked.
0x280[1] RO pll_cal_busy Indicates the calibration status. 1'b1 indicates the PLL is currently being calibrated.
0x280[2] RO avmm_busy Shows the status of the internal configuration bus arbitration. 1’b1 indicates PreSICE has control of the internal configuration bus. 1'b0 indicates the user has control of the internal configuration bus. Refer to the Arbitration section for more details.

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