Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

3.9.1.1. x6/xN Bonding

In x6/xN bonding mode, a single transmit PLL is used to drive multiple channels.

The steps below explain the x6/xN bonding process:

  1. The ATX PLL or the fPLL generates a high speed serial clock.
  2. The PLL drives the high speed serial clock to the master CGB via the x1 clock network.
  3. The master CGB drives the high speed serial and the low speed parallel clock into the x6 clock network.
  4. The x6 clock network feeds the TX clock multiplexer for the transceiver channels within the same transceiver bank. The local CGB in each transceiver channel is bypassed.
  5. To drive the channels in adjacent transceiver banks, the x6 clock network drives the xN clock network. The xN clock network feeds the TX clock multiplexer for the transceiver channels in these adjacent transceiver banks.

x6/xN Bonding Disadvantages

x6/xN Bonding has the following disadvantages:
  • The maximum data rate is restricted based on the transceiver supply voltage. Refer to Arria 10 Device Data Sheet.
  • The maximum channel span is limited to two transceiver banks above and below the bank containing the transmit PLL. Thus, the maximum span of 30 channels is supported.

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