Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

6.7. Recommendations for Dynamic Reconfiguration

Recommendations for TX PLLs

Intel recommends you control pll_powerdown for the fPLL through the soft registers in the following cases:

  • Reconfiguring fPLL from integer mode to fractional mode
  • Reconfiguring fPLL within fractional mode from one rate to another

For all other reconfiguration scenarios, do not hold the PLL in reset before and during reconfiguration.

When reconfiguring across data rates or protocol modes, Intel recommends that you hold the channel transmitter (analog and digital) associated with the PLL in reset during reconfiguration and recalibration of the PLL.You can use the tx_digitalreset, rx_digitalreset, tx_analogreset, and rx_analogreset ports or use the channel soft register for digital and analog resets. For details about placing the channel in analog reset, refer to the "Model 1: Default Model" and "Model 2: Acknowledgment Model" sections of the Resetting Transceiver Channels chapter.

Note: If you need to reconfigure the ATX PLL, use TX PLL switching mode or use local clock divider to achieve new data rate to avoid recalibrating the ATX PLL. Refer to "ATX PLL Usage Guideline" in the "PLLs and Clock Networks" chapter for more details.

Recommendations for Channels

  • When reconfiguring across data rates or protocol modes, Intel recommends that you hold the channel transmitter (analog and digital) in reset during reconfiguration and recalibration of the channel transmitter. You can use the tx_digitalreset, rx_digitalreset, tx_analogreset, and rx_analogreset ports or use the channel soft register for digital and analog resets. For details about placing the channel in analog reset, refer to the "Model 1: Default Model" and "Model 2: Acknowledgment Model" sections of the Resetting Transceiver Channels chapter.
  • When reconfiguring across data rates or protocol modes, Intel recommends that you hold the channel receiver (analog and digital) in reset during reconfiguration and recalibration of the channel receiver. You can use the tx_digitalreset, rx_digitalreset, tx_analogreset, and rx_analogreset ports or use the channel soft register for digital and analog resets. For details about placing the channel in analog reset, refer to the "Model 1: Default Model" and "Model 2: Acknowledgment Model" sections of the Resetting Transceiver Channels chapter.
  • When performing reconfiguration on channels not involving data rate or protocol mode change, Intel recommends that you hold the channel transmitter (digital only) in reset during reconfiguration.
  • When performing reconfiguration on channels not involving data rate or protocol mode change, Intel recommends that you hold the channel receiver (digital only) in reset during reconfiguration.

Refer to the Arria® 10 Transceiver Register Map for detailed information about the soft registers for PLL powerdown.

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