Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Public
Document Table of Contents

2.6.5.5.1. Clock and Reset Signals

Table 160.  Clock and Reset Signals
Signal Name Direction Width Description
Clock signals
tx_clkout

Output

1

GMII TX clock, derived from tx_serial_clk[1:0]. Provides 156.25 MHz timing reference for 2.5GbE; 62.5 MHz for 1GbE.

rx_clkout

Output

1

GMII RX clock, derived from tx_serial_clk[1:0]. Provides 156.25 MHz timing reference for 2.5GbE; 62.5 MHz for 1GbE.

csr_clk

Input

1

Clock for the control and status Avalon® memory-mapped interface. Intel recommends 125 – 156.25 MHz for this clock.