Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.4.6.7. MII

Table 141.  MII Signals
Name Direction Description
MII Transmit Interface
mii_tx_d[3:0] Input MII transmit data bus.
mii_tx_en Input Assert this signal to indicate that the data on mii_tx_d[3:0]is valid.
mii_tx_err Input Assert this signal to indicate to the PHY device that the frame sent is invalid.
MII Receive Interface
mii_rx_d[3:0] Output MII receive data bus.
mii_rx_dv Output Asserted to indicate that the data on mii_rx_d[3:0]is valid. The signal stays asserted during frame reception, from the first preamble byte until the last byte of the CRC field is received.
mii_rx_err Output Asserted by the PHY to indicate that the current frame contains errors.
mii_col Output Collision detection. Asserted by the PCS function to indicate that a collision was detected during frame transmission.
mii_crs Output Carrier sense detection. Asserted by the PCS function to indicate that a transmit or receive activity is detected on the Ethernet line.

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