Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.7.14. Using Transceiver Toolkit (TTK)/System Console/Reconfiguration Interface to manually tune Arria® 10 PCIe designs (Hard IP(HIP) and PIPE) (For debug only)

Table 199.  Manual tuning of TX analog settings for PCIe channelsTo manually tune TX channels of the Arria® 10 PCIe designs using TTK/System Console/Reconfiguration Interface, you must set the following attributes
Attribute Default value in PCIe mode Value to be set to use TTK/System Console Description

user_fir_coeff_ctrl_sel 0x105[7]

1’b1

1’b0

Mux to select between static vs dynamic (port) control
  • 0 for static setting (to use TTK/system console for manual tuning)
  • 1 for dynamic control (PCIe mode)

Setting this mux affects VOD, pre tap and post tap attributes

pre_emp_switching_ctrl_pre_tap_1t 0x107[4:0]

Controlled by coefficients on the port pipe_g3_txdeemph

Depends on value set by pre_emp_switching_ctrl_pre_tap_1t register setting

Sets 1st Pre tap value
  • Direct mapped

pre_emp_sign_pre_tap_1t 0x107[5]

negative

Depends on value set by pre_emp_sign_pre_tap_1t register setting

Sets 1st Pre tap sign
  • - 1 negative (default for PCIe mode)
  • 0 positive

vod_output_swing_ctrl 0x109[4:0]

Controlled by coefficients on the port pipe_g3_txdeemph

Depends on value set by vod_output_swing_ctrl register setting

Output swing
  • Direct mapped

pre_emp_switching_ctrl_1st_post_tap 0x105[4:0]

Controlled by coefficients on the port pipe_g3_txdeemph

Depends on value set by pre_emp_switching_ctrl_1st_post_tap register setting

Sets 1st Post tap value
  • Direct mapped

pre_emp_sign_1st_post_tap 0x105[6]

Negative

Depends on value set by pre_emp_sign_1st_post_tapregister setting

Set 1st Post tap sign
  • - 1 negative (default for PCIe mode)
  • - 0 positive
Note: You must set the attribute user_fir_coeff_ctrl_sel located at register address 0x105[7] back to 1’b1 to allow the Arria® 10 PCI Express PIPE design to listen to the port pipe_g3_txdeemph[17:0] on each channel for normal PCIe operation.
Table 200.  Manual tunning of RX analog settings for PCIe channelsTo manually tune RX channels of the Arria® 10 PCI Express designs using TTK/System Console/Reconfiguration Interface, you must set the following attribute
Attribute Default value in PCIe mode Value to be set to use TTK/System Console Description

rrx_pcie_eqz 0x161[2]

1’b1

1’b0

Mux to select between static vs dynamic control
  • 0 for static setting (use for manual tuning)
  • 1 for dynamic control (PCIe mode)

Setting this mux affects the CTLE 4s gain and 1s gain values

adp_4s_ctle_bypass 0x167[0]

1’b0

  • 1’b0 for Gen3 for Adaptive 4S CTLE
  • 1’b1 for Gen1/Gen2 for Manual 4S CTLE
Mux to select between CTLE 4S manual mode vs adaptive mode
  • 0 for CTLE 4S adaptive mode
  • 1 for CTLE 4S manual mode

adp_ctle_acgain_4s 0x167[5:1]

5’b0

Depends on the value set by adp_ctle_acgain_4s Register setting

Set CTLE manual 4S AC gain
  • Direct mapped

Adp_status_sel 0x14C[5:0]

Set the mux to 6’b011011

Set the mux to 6’b011011

Sets the test mux to read the CTLE converged values from 0x177[3:0]

Test_mux 0x177[3:0]

Read values. Map 4 bit value read out to 5 bit gain values

Read values. Map 4 bit value read out to 5 bit gain values

Reflects the converged values from CTLE adaptation
Note: You must set the attribute rrx_pcie_eqz located at register address 0x161[2] back to 1’b1 to allow the Arria® 10 PCIe PIPE design to listen to the port pipe_g3_rxpresethint[2:0] on each channel for normal PCIe operation.

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