Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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4.6. Combining Status or PLL Lock Signals

You can combine multiple PHY status signals before feeding into the reset controller as shown below.
Figure 220. Combining Multiple PHY Status Signals


Note: This configuration also applies to the rx_cal_busy signals.

When using multiple PLLs, you can logical AND the pll_locked signals feeding the reset controller. Similarly, you can logical OR the pll_cal_busy signals to the reset controller tx_cal_busy port as shown below.

Figure 221. Multiple PLL Configuration


Resetting different channels separately requires multiple reset controllers. For example, a group of channels configured for Interlaken requires a separate reset controller from another group of channels that are configured for optical communication.

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