Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

5.3.2.1.1. Word Aligner Bit Slip Mode

In bit slip mode, the word aligner operation is controlled by rx_bitslip, which has to be held for two parallel clock cycles. At every rising edge of rx_bitslip, the bit slip circuitry slips one bit into the received data stream, effectively shifting the word boundary by one bit. Pattern detection is not used in bit slipping mode; therefore, rx_syncstatus is not valid in this mode.

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