Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.9.2.8. Rate Match FIFO Basic (Double Width) Mode

  1. Select basic (double width) in the RX rate match FIFO mode list.
  2. Enter values for the following parameters.
    Parameter Value Description
    RX rate match insert/delete +ve pattern (hex) 20 bits of data specified as a hexadecimal string The first 10 bits correspond to the skip pattern and the last 10 bits correspond to the control pattern. The skip pattern must have neutral disparity.
    RX rate match insert/delete -ve pattern (hex) 20 bits of data specified as a hexadecimal string The first 10 bits correspond to the skip pattern and the last 10 bits correspond to the control pattern. The skip pattern must have neutral disparity.

    The rate match FIFO can delete as many pairs of skip patterns from a cluster as necessary to avoid the rate match FIFO from overflowing. The rate match FIFO can delete a pair of skip patterns only if the two 10-bit skip patterns appear in the same clock cycle on the LSByte and MSByte of the 20-bit word. If the two skip patterns appear straddled on the MSByte of a clock cycle and the LSByte of the next clock cycle, the rate match FIFO cannot delete the pair of skip patterns.

    In the following figure, the first skip cluster has a /K28.5/ control pattern in the LSByte and /K28.0/ skip pattern in the MSByte of a clock cycle followed by one /K28.0/ skip pattern in the LSByte of the next clock cycle. The rate match FIFO cannot delete the two skip patterns in this skip cluster because they do not appear in the same clock cycle. The second skip cluster has a /K28.5/ control pattern in the MSByte of a clock cycle followed by two pairs of /K28.0/ skip patterns in the next two cycles. The rate match FIFO deletes both pairs of /K28.0/ skip patterns (for a total of four skip patterns deleted) from the second skip cluster to meet the three skip pattern deletion requirement.

    The rate match FIFO can insert as many pairs of skip patterns into a cluster necessary to avoid the rate match FIFO from under running. The 10-bit skip pattern can appear on the MSByte, the LSByte, or both, of the 20-bit word.

    Figure 148. Rate Match FIFO Deletion with Four Skip Patterns Required for Deletion/K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern.


    In the following figure, /K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a /K28.5/ control pattern in the LSByte and /K28.0/ skip pattern in the MSByte of a clock cycle. The rate match FIFO inserts pairs of skip patterns in this skip cluster to meet the three skip pattern insertion requirement.

    Figure 149. Rate Match FIFO Insertion with Four Skip Patterns Required for Insertion


    The following figure shows the deletion of the 20-bit word D7D8.

    Figure 150.  Rate Match FIFO Becoming Full After Receiving the 20-Bit Word D5D6


    The following figure shows the insertion of two skip symbols.

    Figure 151. Rate Match FIFO Becoming Empty After Reading out the 20-Bit Word D5D6


Did you find the information on this page useful?

Characters remaining:

Feedback Message