Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Public
Document Table of Contents

2.9.2.8. Rate Match FIFO Basic (Double Width) Mode

  1. Select basic (double width) in the RX rate match FIFO mode list.
  2. Enter values for the following parameters.
    Parameter Value Description
    RX rate match insert/delete +ve pattern (hex) 20 bits of data specified as a hexadecimal string The first 10 bits correspond to the skip pattern and the last 10 bits correspond to the control pattern. The skip pattern must have neutral disparity.
    RX rate match insert/delete -ve pattern (hex) 20 bits of data specified as a hexadecimal string The first 10 bits correspond to the skip pattern and the last 10 bits correspond to the control pattern. The skip pattern must have neutral disparity.

    The rate match FIFO can delete as many pairs of skip patterns from a cluster as necessary to avoid the rate match FIFO from overflowing. The rate match FIFO can delete a pair of skip patterns only if the two 10-bit skip patterns appear in the same clock cycle on the LSByte and MSByte of the 20-bit word. If the two skip patterns appear straddled on the MSByte of a clock cycle and the LSByte of the next clock cycle, the rate match FIFO cannot delete the pair of skip patterns.

    In the following figure, the first skip cluster has a /K28.5/ control pattern in the LSByte and /K28.0/ skip pattern in the MSByte of a clock cycle followed by one /K28.0/ skip pattern in the LSByte of the next clock cycle. The rate match FIFO cannot delete the two sk