Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.7.10. ATX PLL Ports for PIPE

Table 194.  ATX PLL Ports for PIPEThis section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter settings.
Port Direction Clock Domain Description
Pll_powerdown Input Asynchronous

Resets the PLL when asserted high. Needs to be connected to a dynamically controlled signal (the Transceiver PHY Reset Controller pll_powerdown output if using this Intel® FPGA IP.

Pll_reflck0 Input N/A

Reference clock input port 0. There are five reference clock input ports. The number of reference clock ports available depends on the Number of PLL reference clocks parameter.

tx_serial_clk Output N/A

High speed serial clock output port for GX channels. Represents the x1 clock network.

For Gen1x1, Gen2x1, connect the output from this port to the tx_serial_clk input of the native PHY IP.

For Gen1x2, x4, x8, use the tx_bonding_clocks output port to connect to the Native PHY.

For Gen2x2, x4, x8, use the tx_bonding_clocks output port to connect to the Native PHY.

For Gen3x1, connect the output from this port to one of the two tx_serial_clk input ports on the native PHY IP.

For Gen3x2, x4, x8, this port is not used. Use the tx_serial_clk output from the fPLL to drive the Auxiliary Master CGB clock input port of the ATX PLL.

pll_locked Output Asynchronous

Active high status signal which indicates if PLL is locked.

pll_pcie_clk Output N/A

This is the hclk required for PIPE interface.

For Gen1x1,x2,x4,x8 use this port to drive the hclk for the PIPE interface.

For Gen2x1,x2,x4,x8 use this port to drive the hclk for the PIPE interface.

For Gen3x1,x2,x4,x8, this port is not used. Use the pll_pcie_clk from fPLL (configured as Gen1/Gen2) as the hclk for the PIPE interface.

Pll_cal_busy