Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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4.3.1.2. Resetting the Transmitter During Device Operation

Follow this reset sequence to reset the PLL or the analog or digital blocks of the transmitter at any point during the device operation. Use this reset sequence to reestablish a link or after dynamic reconfiguration. The following steps detail the transmitter reset sequence during device operation. The step numbers correspond to the numbers in the following figure.
  1. Perform the following steps:
    1. Assert tx_analogreset, pll_powerdown, and tx_digitalreset while pll_cal_busy and tx_cal_busy are low.
    2. Deassert pll_powerdown after a minimum duration of 1 μs. This step can be delayed and deasserted at the same time you deassert tx_analogreset.
    3. Deassert tx_analogreset after a minimum duration of 70 μs.
  2. The pll_locked signal goes high after the TX PLL acquires lock. Wait for a minimum of 70 μs after deasserting tx_analogreset to monitor the pll_locked signal.
  3. Deassert tx_digitalreset, after pll_locked goes high. The tx_digitalreset signal must stay asserted for a minimum ttx_digitalreset duration after tx_analogreset is deasserted.
    Note: You must reset the PCS blocks by asserting tx_digitalreset, every time you assert pll_powerdown and tx_analogreset.
Figure 204. Transmitter Reset Sequence During Device Operation

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