Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.6.4.8. Creating a 1G/10GbE Design

Follow these steps to create a 1G/10GbE design using the 1G/10GbE PHY IP.
  1. Generate the 1G/10GbE PHY with the required parameterization.
    The 1G/10GbE PHY IP Core includes reconfiguration logic. This logic provides the Avalon® memory-mapped interface that you can use to read and write to PHY registers. All read and write operations must adhere to the Avalon specification.
  2. Instantiate a reset controller using the Transceiver Reset Controller Intel® FPGA IP Core in the IP Catalog. Connect the power and reset signals between the 1G/10GbE PHY and the reset controller.
  3. Instantiate one TX PLL for the 1G data rate and one TX PLL for the 10G data rate. Connect the high speed serial clock and PLL lock signals between 1G/10GbE PHY and TX PLLs. You can use any combination of fPLLs, ATX, or CMU PLLs.
  4. Use the tx_pma_divclk from 1G/10GbE PHY or generate a fPLL to create the 156.25 MHz XGMII clock from the 10G reference clock.
    No Memory Initialization Files (.mif) are required for the 1G/10GbE design in Arria 10 devices.
  5. Complete the design by creating a top level module to connect all the IP (1G/10GbE PHY IP, PLL IP and Reset Controller) blocks.

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