Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

2.6.4.8. Creating a 1G/10GbE Design

Follow these steps to create a 1G/10GbE design using the 1G/10GbE PHY IP.
  1. Generate the 1G/10GbE PHY with the required parameterization.
    The 1G/10GbE PHY IP Core includes reconfiguration logic. This logic provides the Avalon® memory-mapped interface that you can use to read and write to PHY registers. All read and write operations must adhere to the Avalon specification.
  2. Instantiate a reset controller using the Transceiver Reset Controller