Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.3.6.3. Enhanced PCS Registers

Table 123.   Enhanced PCS Registers
Addr Bit Access Name Description
0x480 31:0 RW Indirect_addr Because the PHY implements a single channel, this register must remain at the default value of 0 to specify logical channel 0.
0x481 2 RW RCLR_ERRBLK_CNT Error block counter clear register. When set to 1, clears the error block counter. When set to 0, normal operation continues.
3 RW RCLR_BER_COUNT BER counter clear register. When set to 1, clears the BER counter. When set to 0, normal operation continues.
0x482 1 RO HI_BER High BER status. When set to 1, the PCS reports a high BER. When set to 0, the PCS does not report a high BER.
2 RO BLOCK_LOCK Block lock status. When set to 1, the PCS is locked to received blocks. When set to 0, the PCS is not locked to received blocks.
3 RO TX_FIFO_FULL When set to 1, the TX_FIFO is full.
4 RO RX_FIFO_FULL When set to 1, the RX_FIFO is full.
7 RO Rx_DATA_READY When set to 1, indicates the PHY is ready to receive data.

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