Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents

7.2.3. Fractional PLL Calibration Registers

Table 298.  Fractional PLL Calibration Registers
Bit fPLL Calibration Enable Register Offset Address 0x100
0 Reserved
1 fPLL calibration enable. Set 1 to enable calibration.

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