Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents
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2.4.4. Enhanced PCS Parameters

This section defines parameters available in the Native PHY IP core GUI to customize the individual blocks in the Enhanced PCS.

The following tables describe the available parameters. Based on the selection of the Transceiver Configuration Rule , if the specified settings violate the protocol standard, the Native PHY IP core Parameter Editor prints error or warning messages.

Note: For detailed descriptions about the optional ports that you can enable or disable, refer to the Enhanced PCS Ports section.
Table 17.  Enhanced PCS Parameters
Parameter Range Description
Enhanced PCS / PMA interface width 32, 40, 64 Specifies the interface width between the Enhanced PCS and the PMA.
FPGA fabric /Enhanced PCS interface width