Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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6.12.2. Changing CTLE Settings in Manual Mode Using Direct Reconfiguration Flow

You can use the reconfiguration interface on the Transceiver Native PHY IP core to change the CTLE settings in manual mode.

  1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic Reconfiguration.
  2. Read from the CTLE feature address of the channel you want to change. For example, to change CTLE AC gain in high gain mode, read and store the value of address 0x167[5:1].
  3. Select a valid value for the feature according to the Arria® 10 register map. For example, a valid setting for CTLE AC Gain has a bit encoding of 5’b00000.
  4. Perform a read-modify-write to the address of the CTLE feature using the valid value. For example, to change the CTLE AC gain in high gain mode, write 5’b00000 to address 0x167[5:1].
  5. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic Reconfiguration.
Table 275.  Register Map for CTLE Settings
CTLE Feature Address Bits Values Description
One Stage Enable 0x11B [3]

1’b0- Selects Four Stage

1’b1- Selects One Stage

Selects the equalizer path as either One Stage or Four Stage mode.
DC Gain 0x11C, 0x11A [3:0], [7:0] 12’b000000000000 12’b111000000000 12’b111111000000 12’b111111111000 12’b111111111111 Sets the DC gain values. This register can only be controlled when in Four stage mode.
CTLE AC Gain One Stage 0x166 [4:1] 4’b0000- 4’b1111 Sets the AC gain value when one stage mode (High data rate mode) is selected. A higher value means higher peaking by suppressing DC gain.
CTLE AC Gain Four Stage 0x167 [5:1] 5’b00000 – 5’b11100 Sets the AC gain value when four stage mode (High gain mode) is selected.
VGA SEL 0x160 [3:1] 3’b000 – 3’b111 Sets the VGA Gain value

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