22.214.171.124.2. SDR XGMII RX Interface
Contains 4 lanes of data and control for XGMII. Each lane consists of 16 bits of data and 2 bits of control. Synchronous to mgmt_clk.
|The XGMII SDR RX clock which runs at 156.25 MHz.|
|xgmii_rx_inclk||Input||The XGMII SDR RX input clock which runs at 156.25 MHz. This port is only available when Enable phase compensation FIFO is selected.|
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