Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

2.6.6.9.2. SDR XGMII RX Interface

Table 174.  SDR RX XGMII Interface
Signal Name Direction Description
xgmii_rx_dc_[71:0]

Output

Contains 4 lanes of data and control for XGMII. Each lane consists of 16 bits of data and 2 bits of control. Synchronous to mgmt_clk.

  • Lane 0–[7:0]/[8], [43:36]/[44]
  • Lane 1–[16:9]/[17], [52:45]/[53]
  • Lane 2–[25:18]/[26], &lbra