Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.6.4.6.2. Data Interfaces

Table 135.  XGMII SignalsThe MAC drives the TX XGMII signals to the 10GbE PHY. The 10GbE PHY drives the RX XGMII signals to the MAC.
Signal Name Direction Clock Domain Description
10GbE XGMII Data Interface
xgmii_tx_dc[71:0]

Input

Synchronous to

xgmii_tx_clk

XGMII data and control for 8 lanes. Each lane consists of 8 bits of data and 1 bit of control.

xgmii_tx_clk

Input

Clock signal

Clock for single data rate (SDR) XGMII TX interface to the MAC. It should connect to xgmii_rx_clk. This clock can be connected to the tx_div_clkout; however, Intel recommends that you connect it to a PLL for use with the Triple Speed Ethernet IP function. The frequency is 125 MHz for 1G and 156.25 MHz for 10G. This clock is driven from the MAC.

The frequencies are the same whether or not you enable FEC.

xgmii_rx_dc[71:0]

Output

Synchronous to

xgmii_rx_clk

RX XGMII data and control for 8 lanes. Each lane consists of 8 bits of data and 1 bit of control.

xgmii_rx_clk

Input

Clock signal

Clock for SDR XGMII RX interface to the MAC. This clock can be connected to the tx_div_clkout ; however, Intel recommends that you connect it to a PLL for use with the Triple Speed Ethernet IP function. The frequency is 125 MHz for 1G and 156.25 MHz for 10G. This clock is driven from the MAC.

The frequencies are the same whether or not you enable FEC.

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