220.127.116.11.2. Data Interfaces
|Signal Name||Direction||Clock Domain||Description|
|10GbE XGMII Data Interface|
XGMII data and control for 8 lanes. Each lane consists of 8 bits of data and 1 bit of control.
Clock for single data rate (SDR) XGMII TX interface to the MAC. It should connect to xgmii_rx_clk. This clock can be connected to the tx_div_clkout; however, Intel recommends that you connect it to a PLL for use with the Triple Speed Ethernet IP function. The frequency is 125 MHz for 1G and 156.25 MHz for 10G. This clock is driven from the MAC.
The frequencies are the same whether or not you enable FEC.