Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.5.4.2. Configuration Registers

You can access the 16 -/ 32-bit configuration registers via the Avalon® memory-mapped interface. The 16-bit configuration registers apply only to 2.5G, 1G/2.5G, and 1G/2.5G/10G (MGBASE-T) operating modes, whereas the 32-bit configuration registers apply only to 10M/100M/1G/2.5G/5G/10G (USXGMII) operating mode.

Observe the following guidelines when accessing the registers:

  • Do not write to reserved or undefined registers.
  • When writing to the registers, perform read-modify-write to ensure that reserved or undefined register bits are not overwritten.
Table 158.  Types of Register Access
Access Definition
RO Read only.
RW Read and write.
RWC Read, and write and clear. The user application writes 1 to the register bit(s) to invoke a defined instruction. The IP core clears the bit(s) upon executing the instruction.
Table 159.  PHY Register Definitions
Addr Name Description Access HW Reset Value

0x00

control
  • Bit [15]: RESET. Set this bit to 1 to trigger a soft reset.

    The PHY clears the bit when the reset is completed. The register values remain intact during the reset.

RWC

0
  • Bit[14]: LOOPBACK. Set this bit to 1 to enable loopback on the serial interface.
RW 0
  • Bit [12]: AUTO_NEGOTIATION_ENABLE. Set this bit to 1 to enable auto-negotiation.

    Auto-negotiation is supported only in 1GbE. Therefore, set this bit to 0 when you switch to a speed other than 1GbE.

RW 0
  • Bit [9]: RESTART_AUTO_NEGOTIATION. Set this bit to 1 to restart auto-negotiation.

    The PHY clears the bit as soon as auto-negotiation is restarted.

RWC 0
  • The rest of the bits are reserved.

0x01

status
  • Bit [5]: AUTO_NEGOTIATION_COMPLETE. A value of "1" indicates that the auto-negotiation is completed.

RO

0
  • Bit [3]: AUTO_NEGOTIATION_ABILITY. A value of "1" indicates that the PCS function supports auto-negotiation.
RO 1
  • Bit [2]: LINK_STATUS. A value of "0" indicates that the link is lost. Value of 1 indicates that the link is established.
RO 0
  • The rest of the bits are reserved.

0x02:0x03

phy_identifier

The value set in the PHY_IDENTIFIER parameter.

RO

Value of PHY_IDENTIFIER parameter

0x04

dev_ability Use this register to advertise the device abilities during auto-negotiation.
  • Bits [13:12]: RF. Specify the remote fault.
    • 00: No error.
    • 01: Link failure.
    • 10: Offline.
    • 11: Auto-negotiation error.
RW 00
  • Bits [8:7]: PS. Specify the PAUSE support.
    • 00: No PAUSE.
    • 01: Symmetric PAUSE.
    • 10: Asymmetric PAUSE towards the link partner.
    • 11: Asymmetric and symmetric PAUSE towards the link device.
RW 11
  • Bit [5]: FD. Ensure that this bit is always set to 1.
RW 1
  • The rest of the bits are reserved.
0x05 partner_ability The device abilities of the link partner during auto-negotiation.
  • Bit [14]: ACK. A value of "1" indicates that the link partner has received three consecutive matching ability values from the device.
RO 0
  • Bits [13:12]: RF. The remote fault.
    • 00: No error.
    • 01: Link failure.
    • 10: Offline.
    • 11: Auto-negotiation error.</