Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents

3.4. Clock Generation Block

In Arria 10 devices, there are two types of clock generation blocks (CGBs)

  • Local clock generation block (local CGB)
  • Master clock generation block (master CGB)

Each transmitter channel has a local clock generation block (CGB). For non-bonded channel configurations, the serial clock generated by the transmit PLL drives the local CGB of each channel. The local CGB generates the parallel clock used by the serializer and the PCS.

There are two standalone master CGBs within each transceiver bank. The master CGB provides the same functionality as the local CGB within each transceiver channel. The output of the master CGB can be routed to other channels within a transceiver bank using the x6 clock lines. The output of the master CGB can also be routed to channels in other transceiver banks using the xN clock lines. Each transmitter channel has a multiplexer to select its clock source from either the local CGB or the master CGB.

Figure 179. Clock Generation Block and Clock NetworkThe local clock for each transceiver channel can be sourced from either the local CGB via the x1 network, or the master CGB via the x6/xN network. For example, as shown by the red highlighted path, the fPLL 1 drives the x1 network which in turn drives the master CGB. The master CGB then drives the x6 clock network which routes the clocks to the local channels. As shown by the blue highlighted path, the ATX PLL 0 can also drive the x1 clock network which can directly feed a channel's local CGB. In this case, the low speed parallel clock is generated by the local CGB.

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