Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Document Table of Contents

3.12. PLLs and Clock Networks Revision History

Document Version Changes
2021.06.10 Added the PCS Bonding Channels Placement Restrictions section.
2021.01.29 Made the following change:
  • To implement fPLL to fPLL cascading, set the destination (downstream) fPLL bandwidth to Low.
2019.05.13 Made the following change: