Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

6.12.4. Enabling and Disabling Loopback Modes Using Direct Reconfiguration Flow

Arria® 10 devices have three loopback modes:

  • Serial Loopback
  • Reverse Serial Loopback (Pre-CDR)
  • Reverse Serial Loopback (Post-CDR)

The loopback mode can be dynamically reconfigured by accessing the register space.

Serial Loopback Mode

In serial loopback mode, a path exists between the serializer of the transmitter and the CDR of the receiver, so that the data from the CDR is recovered from the serializer while the data from the receiver serial input pin is ignored. You can enable or disable this mode.

Figure 275. Serial Loopback Mode

To enable serial loopback mode:

  1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic Reconfiguration.
  2. Perform a read-modify-write to address 0x2E1 to set bit 0 to 1’b1
  3. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic Reconfiguration.

To disable serial loopback mode:

  1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic Reconfiguration.
  2. Perform a read-modify-write to address 0x2E1 to set bit 0 to 1’b0
  3. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic Reconfiguration.

You can also enable the serial loopback mode by turning on Enable rx_seriallpbken port in the Native PHY IP Parameter Editor and driving the port to 1’b1.

Reverse Serial Loopback Mode (Pre-CDR)

In the pre-CDR mode, data received through the RX input buffer is looped back to the TX output buffer. You can enable the reverse serial loopback mode by performing read-modify-write to the following registers.

Figure 276. Reverse Serial Loopback Mode (Pre-CDR)
Table 277.  Bit Values to Be Set
Address Bit Values
0x137[7] 1’b1
0x13C[7] 1’b0
0x132[5:4] 2’b00
0x142[4] 1’b1
0x11D[0] 1’b1

Reverse Serial Loopback Mode (Post-CDR)

In the post-CDR mode, received data passes through the RX CDR and then loops back to the TX output buffer. Perform read-modify-write to the following registers to enable this mode.

Figure 277. Reverse Serial Loopback Mode (Post-CDR)
Table 278.  Bit Values to Be Set
Address Bit Values
0x137[7] 1’b0
0x13C[7] 1’b1
0x132[5:4] 2’b01
0x142[4] 1’b0
0x11D[0] 1’b0

Disabling Reverse Serial Loopback Mode (Pre-CDR and Post-CDR)

To disable reverse-serial loopback mode, set the address bits to the following values, by performing read-modify-write.

Table 279.  Bit Values to Be Set
Address Bit Values
0x137[7] 1’b0
0x13C[7] 1’b0
0x132[5:4] 2’b00
0x142[4] 1’b0
0x11D[0] 1’b0

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