Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

5.3.2.1.4. Word Aligner Deterministic Latency Mode

In deterministic latency mode, the state machine removes the bit level latency uncertainty. The deserializer of the PMA creates the bit level latency uncertainty as it comes out of reset.

The PCS performs pattern detection on the incoming data from the PMA. The PCS aligns the data, after it indicates to the PMA the number of serial bits to clock slip the boundary.

If the incoming data has to be realigned, rx_std_wa_patternalign must be reasserted to initiate another pattern alignment. Asserting rx_std_wa_patternalign can cause the word align to lose synchronization if already achieved. This may cause rx_syncstatus to go low.

Table 260.  PCS-PMA Interface Widths and Protocol Implementations
PCS-PMA Interface Width Protocol Implementations
8 Basic
10
  • Basic
  • Basic rate match
  • CPRI
  • PCIe* Gen1 and Gen2
  • GigE
16 Basic
20
  • CPRI
  • Basic
  • Basic rate match

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