Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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2.4.3. PMA Parameters

You can specify values for the following types of PMA parameters:

TX PMA
  • TX Bonding Options
  • TX PLL Options
  • TX PMA Optional Ports
RX PMA
  • RX CDR Options
  • Equalization
  • RX PMA Optional Ports
Table 11.  TX Bonding Options
Parameter Value Description
TX channel bonding mode

Not bonded

PMA only bonding

PMA and PCS bonding

Selects the bonding mode to be used for the channels specified. Bonded channels use a single TX PLL to generate a clock that drives multiple channels, reducing channel-to-channel skew. The following options are available:

Not bonded: In a non-bonded configuration, only the high speed serial clock is expected to be connected from the TX PLL to the Native PHY IP core. The low speed parallel clock is generated by the local clock generation block (CGB) present in the transceiver channel. For non-bonded configurations, because the channels are not related to each other and the feedback path is local to the PLL, the skew between channels cannot be calculated.

PMA only bonding: In PMA bonding, the high speed serial clock is routed from the transmitter PLL to the master CGB. The master CGB generates the high speed and low parallel clocks and the local CGB for each channel is bypassed. Refer to the Channel Bonding section for more details.

PMA and PCS bonding : In a PMA and PCS bonded configuration, the local CGB in each channel is bypassed and the parallel clocks generated by the master CGB are used to clock the network. The master CGB generates both the high and low speed clocks. The master channel generates the PCS control signals and distributes to other channels through a control plane block.

The default value is Not bonded.

Refer to Channel Bonding section in PLLs and Clock Networks chapter for more details.
PCS TX channel bonding master Auto, 0 to <number of channels> -1

Specifies the master PCS channel for PCS bonded configurations. Each Native PHY IP core instance configured with bonding must specify a bonding master. If you select Auto, the Native PHY IP core automatically selects a recommended channel.

The default value is Auto. Refer to the PLLs and Clock Networks chapter for more information about the TX channel bonding master.

Actual PCS TX channel bonding master 0 to <number of channels> -1

This parameter is automatically populated based on your selection for the PCS TX channel bonding master parameter. Indicates the selected master PCS channel for PCS bonded configurations.

Table 12.  TX PLL Options
Parameter Value Description
TX local clock division factor

1, 2, 4, 8

Specifies the value of the divider available in the transceiver channels to divide the TX PLL output clock to generate the correct frequencies for the parallel and serial clocks.

Number of TX PLL clock inputs per channel

1, 2, 3 , 4

Specifies the number of TX PLL clock inputs per channel. Use this parameter when you plan to dynamically switch between TX PLL clock sources. Up to four input sources are possible.

Initial TX PLL clock input selection

0 to <number of TX PLL clock inputs> -1

Specifies the initially selected TX PLL clock input. This parameter is necessary when you plan to switch between multiple TX PLL clock inputs.
Table 13.  TX PMA Optional Ports
Parameter Value Description
Enable tx_pma_analog_reset_ack port On/Off Enables the optional tx_pma_analog_reset_ack output port. This port should not be used for register mode data transfers.
Enable tx_pma_clkout port On/Off Enables the optional tx_pma_clkout output clock. This is the low speed parallel clock from the TX PMA. The source of this clock is the serializer. It is driven by the PCS/PMA interface block. 24
Enable tx_pma_div_clkout port On/Off Enables the optional tx_pma_div_clkout output clock. This clock is generated by the serializer. You can use this to drive core logic, to drive the FPGA - transceivers interface.

Data rate must be equal or higher than 5 Gbps to enable the use of this clock port.

If you select a tx_pma_div_clkout division factor of 1 or 2, this clock output is derived from the PMA parallel clock. If you select a tx_pma_div_clkout division factor of 33, 40, or 66, this clock is derived from the PMA high serial clock. This clock is commonly used when the interface to the TX FIFO runs at a different rate than the PMA parallel clock frequency, such as 66:40 applications.

tx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66 Selects the division factor for the tx_pma_div_clkout output clock when enabled. 25
Enable tx_pma_iqtxrx_clkout port On/Off Enables the optional tx_pma_iqtxrx_clkout output clock. This clock can be used to cascade the TX PMA output clock to the input of a PLL.
Enable tx_pma_elecidle port On/Off Enables the tx_pma_elecidle port. When you assert this port, the transmitter is forced into an electrical idle condition. This port has no effect when the transceiver is configured for PCI Express*.
Enable tx_pma_qpipullup port (QPI) On/Off Enables the tx_pma_qpipullup control input port. Use this port only for Quick Path Interconnect (QPI) applications.
Enable tx_pma_qpipulldn port (QPI) On/Off Enables the tx_pma_qpipulldn control input port. Use this port only for QPI applications.
Enable tx_pma_txdetectrx port (QPI) On/Off Enables the tx_pma_txdetectrx control input port. The receiver detect block in the TX PMA detects the presence of a receiver at the other end of the channel. After receiving a tx_pma_txdetectrx request the receiver detect block initiates the detection process. Use this port only in QPI applications.
Enable tx_pma_rxfound port (QPI) On/Off Enables the tx_pma_rxfound status output port. The receiver detect block in TX PMA detects the presence of a receiver at the other end by using the tx_pma_txdetectrx input. The tx_pma_rxfound port reports the status of the detection operation. Use this port only in QPI applications.
Enable rx_seriallpbken port On/Off Enables the optional rx_seriallpbken control input port. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This is an asynchronous input signal.
Table 14.  RX CDR Options
Parameter Value Description
Number of CDR reference clocks 1 - 5

Specifies the number of CDR reference clocks. Up to 5 sources are possible.

The default value is 1.

Use this feature when you want to dynamically re-configure CDR reference clock source.

Selected CDR reference clock 0 to <number of CDR reference clocks> -1

Specifies the initial CDR reference clock. This parameter determines the available CDR references used.

The default value is 0.

Selected CDR reference clock frequency < data rate dependent > Specifies the CDR reference clock frequency. This value depends on the data rate specified.
PPM detector threshold

100

300

500

1000

Specifies the PPM threshold for the CDR. If the PPM between the incoming serial data and the CDR reference clock, exceeds this threshold value, the CDR loses lock.

The default value is 1000.

Table 15.  Equalization
Parameters Value Description
CTLE adaptation mode

Manual

Specifies the Continuous Time Linear Equalization (CTLE) operation mode.

For manual mode, set the CTLE options through the Assignment Editor, or modify the Quartus Settings File (.qsf), or write to the reconfiguration registers using the Avalon Memory-Mapped interface.

Refer to Continuous Time Linear Equalization (CTLE) section in Arria® 10 Transceiver Architecture chapter for more details about CTLE architecture. Refer to How to Enable CTLE and DFE for more details on supported adaptation modes.

DFE adaptation mode

Adaptation enabled

Manual, Disabled

Specifies the operating mode for the Decision Feedback Equalization (DFE) block in the RX PMA.

The default value is Disabled.

For manual mode, you can set the DFE options through the Assignment Editor, or by modifying the Quartus Settings File (.qsf), or write to the reconfiguration registers using the Avalon® memory-mapped interface.

Refer to the Decision Feedback Equalization (DFE) section in the Arria® 10 Transceiver PHY Architecture chapter for more details about DFE. Refer to How to Enable CTLE and DFE for more details on supported adaptation modes.

Number of fixed DFE taps 3, 7 , 11 Specifies the number of fixed DFE taps. Select the number of taps depending on the loss in your transmission channel and the type of equalization required.
Table 16.  RX PMA Optional Ports
Parameters Value Description
Enable rx_analog_reset_ack port On/Off Enables the optional rx_analog_reset_ack output. This port should not be used for register mode data transfers.
Enable rx_pma_clkout port On/Off Enables the optional rx_pma_clkout output clock. This port is the recovered parallel clock from the RX clock data recovery (CDR). 26
Enable rx_pma_div_clkout port On/Off Enables the optional rx_pma_div_clkout output clock. The deserializer generates this clock. Use this to drive core logic, to drive the RX PCS-to-FPGA fabric interface, or both.

If you select a rx_pma_div_clkout division factor of 1 or 2, this clock output is derived from the PMA parallel clock. If you select a rx_pma_div_clkout division factor of 33, 40, or 66, this clock is derived from the PMA serial clock. This clock is commonly used when the interface to the RX FIFO runs at a different rate than the PMA parallel clock frequency, such as 66:40 applications.

rx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66 Selects the division factor for the rx_pma_div_clkout output clock when enabled. 27
Enable rx_pma_iqtxrx_clkout port On/Off Enables the optional rx_pma_iqtxrx_clkout output clock. This clock can be used to cascade the RX PMA output clock to the input of a PLL.
Enable rx_pma_clkslip port On/Off Enables the optional rx_pma_clkslip control input port. This signal can be used for word alignment. A falling edge on this signal makes the RX deserializer bit slip the serial data by one unit interval (UI). In rare cases, a two UI slip can occur. When this happens and word alignment detection is not completed, continue slipping until the word alignment detection completes.
Enable rx_pma_qpipulldn port (QPI) On/Off Enables the rx_pma_qpipulldn control input port. Use this port only for QPI applications.
Enable rx_is_lockedtodata port On/Off Enables the optional rx_is_lockedtodata status output port. This signal indicates that the RX CDR is currently in lock to data mode or is attempting to lock to the incoming data stream. This is an asynchronous output signal.
Enable rx_is_lockedtoref port On/Off Enables the optional rx_is_lockedtoref status output port. This signal indicates that the RX CDR is currently locked to the CDR reference clock. This is an asynchronous output signal.
Enable rx_set_lockedtodata port and rx_set_lockedtoref ports On/Off Enables the optional rx_set_lockedtodata and rx_set_lockedtoref control input ports. You can use these control ports to manually control the lock mode of the RX CDR. These are asynchronous input signals.
Enable rx_seriallpbken port On/Off Enables the optional rx_seriallpbken control input port. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This is an asynchronous input signal.
Enable PRBS (Pseudo Random Bit Sequence) verifier control and status port On/Off Enables the optional rx_prbs_err, rx_prbs_clr, and rx_prbs_done control ports. These ports control and collect status from the internal PRBS verifier.
24 This clock should not be used to clock the FPGA - transceivers interface. This clock may be used as a reference clock to an external clock cleaner.
25 The default value is Disabled.
26 This clock should not be used to clock the FPGA - transceiver interface. This clock may be used as a concept clock to an external clock cleaner.
27 The default value is Disabled.

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