Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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3.2.3. PLL Cascading as an Input Reference Clock Source

In PLL cascading, PLL outputs are connected to the feedback and cascading clock network. The input reference clock to the first PLL can be sourced from the same network. In this mode, the output of one PLL drives the reference clock input of another PLL. PLL cascading can generate frequency outputs not normally possible with a single PLL solution. The transceiver in Arria® 10 devices support fPLL to fPLL cascading, with only maximum two fPLLs allowed in the cascading chain. ATX PLL to fPLL cascading is available to OTN and SDI protocols only.
Note:
  • To successfully complete the calibration process, the reference clocks driving the PLLs (ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of FPGA configuration. Otherwise, recalibration is necessary.
  • When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration on the fPLL is required. Refer to "User Recalibration" section in "Calibration" chapter for more information.

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