Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents

6.15.1. Native PHY Debug Master Endpoint

The NPDME is a JTAG-based Avalon® memory-mapped interface master that provides access to the transceiver and PLL registers through the system console. You can enable NPDME using the Enable Native PHY Debug Master Endpoint option available under the Dynamic Reconfiguration tab in the Native PHY and PLL IP cores. When using NPDME, the Quartus Prime software inserts the debug interconnect fabric to connect with USB, JTAG, or other net hosts. Select the Share Reconfiguration Interface parameter when the Native PHY IP instance has more than one channel.

When you enable NPDME in your design, you must

  • connect an Avalon® memory-mapped interface master to the reconfiguration interface.
  • OR connect the, reconfig_reset signals and ground the reconfig_write, reconfig_read, reconfig_address and reconfig_write data signals of the reconfiguration interface. If the reconfiguration interface signals are not connected appropriately, there is no clock or reset for the NPDME, and the NPDME does not function as expected.