Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents 10GBASE-KR PHY Register Definitions

The Avalon® memory-mapped interface slave signals provide access to the control and status registers.

The following table specifies the control and status registers that you can access over the Avalon® memory-mapped interface PHY management. A single address space provides access to all registers.

Note: Unless otherwise indicated, the default value of all registers is 0.
Note: Writing to reserved or undefined register addresses may have undefined side effects.
Table 121.  10GBASE-KR Register Definitions
Word Addr Bit R/W Name Description
0x4B0 0 RW Reset SEQ When set to 1, resets the 10GBASE‑KR sequencer (auto rate detect logic), initiates a PCS reconfiguration, and may restart Auto-Negotiation, Link Training or both if AN and LT are enabled (10GBASE-KR mode). SEQ Force Mode[2:0] forces these modes. This reset self clears.
1 RW Disable AN Timer Auto‑Negotiation disable timer. If disabled ( Disable AN Timer = 1) , AN may get stuck and require software support to remo