Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

2.6.3.6.1. 10GBASE-KR PHY Register Definitions

The Avalon® memory-mapped interface slave signals provide access to the control and status registers.

The following table specifies the control and status registers that you can access over the Avalon® memory-mapped interface PHY management. A single address space provides access to all registers.

Note: Unless otherwise indicated, the default value of all registers is 0.