Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents 10GBASE-KR PHY Register Definitions

The Avalon® memory-mapped interface slave signals provide access to the control and status registers.

The following table specifies the control and status registers that you can access over the Avalon® memory-mapped interface PHY management. A single address space provides access to all registers.

Note: Unless otherwise indicated, the default value of all registers is 0.
Note: Writing to reserved or undefined register addresses may have undefined side effects.
Table 121.  10GBASE-KR Register Definitions
Word Addr Bit R/W Name Description
0x4B0 0 RW Reset SEQ When set to 1, resets the 10GBASE‑KR sequencer (auto rate detect logic), initiates a PCS reconfiguration, and may restart Auto-Negotiation, Link Training or both if AN and LT are enabled (10GBASE-KR mode). SEQ Force Mode[2:0] forces these modes. This reset self clears.
1 RW Disable AN Timer Auto‑Negotiation disable timer. If disabled ( Disable AN Timer = 1) , AN may get stuck and require software support to remove the ABILITY_DETECT capability if the link partner does not include this feature. In addition, software may have to take the link out of loopback mode if the link is stuck in the ACKNOWLEDGE_DETECT state. To enable this timer set Disable AN Timer = 0.
2 RW Disable LF Timer When set to 1, disables the Link Fail timer. When set to 0, the Link Fault timer is enabled.
3 RW fail_lt_if_ber When set to 1, the last LT measurement is a non-zero number. Treat this as a failed run. 0 = normal.
7:4 RW SEQ Force Mode[3:0]

Forces the sequencer to a specific protocol. Must write the Reset SEQ bit to 1 for the Force to take effect. The following encodings are defined:

  • 0000: No force
  • 0001: GigE
  • 0010: XAUI
  • 0100: 10GBASE-R
  • 0101: 10GBASE-KR
  • 1100: 10GBASE-KR FEC
8 RW Enable Arria 10 Calibration When set to 1, it enables the Arria 10 HSSI reconfiguration calibration as part of the PCS dynamic reconfiguration. 0 skips the calibration when the PCS is reconfigured.
11:9 RW Reserved
12 RW LT failure response When set to 1, LT failure causes the PHY to go into data mode. When set to 0, LT failure restarts auto-negotiation (if enabled). If auto-negotiation is not enabled, the PHY restarts LT.
16 RW KR FEC enable 171.0 When set to 1, FEC is enabled. When set to 0, FEC is disabled. Resets to the CAPABLE_FEC parameter value.
17 RW KR FEC enable err ind 171.1 When set to 1, KR PHY FEC decoding errors are signaled to the PCS. When set to 0, FEC errors are not signaled to the PCS. See Clause 74.8.3 of IEEE 802.3ap-2007 for details.
18 RW KR FEC request When set to 1, enables the FEC request. When this bit changes, you must assert the Reset SEQ bit (0x4B0[0]) to renegotiate with the new value. When set to 0, disables the FEC request.
0x4B1 0 R SEQ Link Ready When asserted, the sequencer is indicating that the link is ready.
1 R SEQ AN timeout When asserted, the sequencer has had an Auto Negotiation timeout. This bit is latched and is reset when the sequencer restarts Auto Negotiation.
2 R SEQ LT timeout When set, indicates that the Sequencer has had a timeout.
13:8 R SEQ Reconfig Mode[5:0] Specifies the Sequencer mode for PCS reconfiguration. The following modes are defined:
  • Bit 8, mode[0]: AN mode
  • Bit 9, mode[1]: LT Mode
  • Bit 10, mode[2]: 10G data mode
  • Bit 11, mode[3]: GigE data mode
  • Bit 12, mode[4]: Reserved for XAUI
  • Bit 13, mode[5]: 10G FEC mode
16 R KR FEC ability 170.0 When set to 1, indicates that the 10GBASE-KR PHY supports FEC. Set as parameter SYNTH_FEC. For more information, refer to Clause of IEEE 802.3ap-2007.
17 R KR FEC err ind ability 170.0 When set to 1, indicates that the 10GBASE-KR PHY is capable of reporting FEC decoding errors to the PCS. For more information, refer to Clause 74.8.3 of IEEE 802.3ap-2007.
0x4B2 0:10 Reserved
11 RW KR FEC TX Error Insert Writing a 1 inserts one error pulse into the TX FEC depending on the Transcoder and Burst error settings. This bit self clears.
31:12 Reserved
0x4B5 to 0x4BF     Reserved for 40G KR Intentionally left empty for address compatibility with 40G MAC + PHY KR solutions.
0x4C0 0 RW AN enable When set to 1, enables Auto Negotiation function. The default value is 1. For additional information, refer to 7.0.12 in Clause 73.8 Management Register Req