Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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7.2. Calibration Registers

The Arria 10 transceiver PMA and PLLs include the following types of registers for calibration:

  • Avalon® memory-mapped interface arbitration registers
  • Calibration enable registers
  • Capability registers
  • Rate switch flag registers

The Avalon® memory-mapped interface arbitration registers enable you to request internal configuration bus access.

The PMA and PLL calibration enable registers for user recalibration are mapped to offset address 0x100. All calibration enable registers are self-cleared after the calibration process is completed.

The tx_cal_busy, rx_cal_busy, ATX PLL pll_cal_busy, and fPLL pll_cal_busy signals are available from the capability registers.

The rate switch flag registers are only used for CDR rate change.

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