Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

In 10GBASE-R mode, the RX FIFO operates as a clock compensation FIFO. When the block synchronizer achieves block lock, data is sent through the FIFO. Idle ordered sets (OS) are deleted and Idles are inserted to compensate for the clock difference between the RX low speed parallel clock and the FPGA fabric clock (±100 ppm for a maximum packet length of 64,000 bytes).

Idle OS Deletion

Deletion of Idles occurs in groups of four OS (when there are two consecutive OS) until the rx_enh_fifo_pfull flag deasserts. Every word—consisting of a lower word (LW) and an upper word (UW)—is checked for whether it can be deleted by looking at both the current and previous words.

For example, the current LW can be deleted if it is Idle and the previous UW is not a Terminate.

Table 257.   Conditions Under Which a Word Can be DeletedIn this table X=don’t care, T=Terminate, I=Idle, and OS=order set.
Deletable Case Word Previous Current Output
Lower Word 1 UW !T X !T X
LW X I X X
2 UW OS X OS X
LW X OS X X
Upper Word 1 UW X I X X
LW X !T X !T
2 UW X OS X X
LW X OS X OS

If only one word is deleted, data shifting is necessary because the datapath is two words wide. After two words have been deleted, the FIFO stops writing for one cycle and a synchronous flag (rx_control[8]) appears on the next block of 8-byte data. There is also an asynchronous status signal rx_enh_fifo_del, which does not go through the FIFO.

Figure 251.  IDLE Word DeletionThis figure shows the deletion of IDLE words from the receiver data stream.
Figure 252.  OS Word DeletionThis figure shows the deletion of Ordered set words in the receiver data stream.

Idle Insertion

Idle insertion occurs in groups of 8 Idles when the rx_enh_fifo_pempty flag is deasserted. Idles can be inserted following Idles or OS. Idles are inserted in groups of 8 bytes. Data shifting is not necessary. There is a synchronous status rx_enh_fifo_insert signal that is attached to the 8-byte Idles being inserted.

Table 258.  Cases Where Two Idle Words are InsertedIn this table X=don’t care, S=start, OS=order set, I-DS=idle in data stream, and I-In=idle inserted. In cases 3 and 4, the Idles are inserted between the LW and UW.
Case Word Input Output
1 UW I-DS I-DS I-In
LW X X I-In
2 UW OS OS I-In
LW X X I-In
3 UW S I-In S
LW I-DS I-DS I-In
4 UW S I-In S
LW OS OS I-In
Figure 253. IDLE Word InsertionThis figure shows the insertion of IDLE words in the receiver data stream.

Did you find the information on this page useful?

Characters remaining:

Feedback Message