Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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9.4. Troubleshooting Common Errors

Missing High-Speed Link Pin Connections

Check the pin connections to identify high-speed links (tx_p/n and rx_p/n) that are missing. When porting an older design to the latest version of the Intel® Quartus® Prime software, ensure that these connections exist after porting.

Reset Issues

Ensure that the reset input to the Transceiver Native PHY, Transceiver Reset Controller, and Transceiver PLL Intel FPGA IPs is not held active (1'b1) . You also need to ensure the reconfig_reset port in Transceiver Native PHY and Transceiver PLL Intel FPGA IPs is not held active.

Unconnected reconfig_clk

You must connect and drive the reconfig_clk input to the Transceiver Native PHY and Transceiver PLL Intel FPGA IPs. Otherwise, the toolkit does not display the transceiver link channel.

Figure 300. Example Error Message

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