L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.3.3. x24 Clock Lines

The x24 clock lines route the transceiver clocks across multiple transceiver banks within the same transceiver tile.

The master CGB drives the x6 clock lines and the x6 clock lines drive the x24 clock lines. There are two x24 clock lines: x24 Up and x24 Down. x24 Up clock lines route the clocks to transceiver banks located above the current bank. x24 Down clock lines route the clocks to transceiver banks located below the current bank.

The x24 clock lines can be used in both bonded and non-bonded configurations. For bonded configurations, the low-speed parallel clock output of the master CGB is used, while the local CGB within each channel is bypassed. For non-bonded configurations, use the master CGB to provide a high-speed serial clock output to each channel, in case you have multiple channels driven by the same ATX/fPLL, and if the non-bonded channels span across a transceiver bank. A maximum of 24 channels can be used in a single bonded or non-bonded x24 group.

When the banks within a transceiver tile are powered at different voltages (for example, some banks are operating at 1.03 V while other banks are operating at 1.12 V), the x24 clock lines are only allowed to traverse between contiguous banks operating at the same VCCR_GXB and VCCT_GXB voltages. The x24 clock lines crossing boundaries of banks operating at different voltages is not allowed. See the Intel® Stratix® 10 Device Family Pin Connection Guidelines for a description of the transceiver power connection guidelines.

Note: The VCCR_GXB and VCCT_GXB per bank option is not enabled in the Intel® Quartus® Prime software by default. Use the following QSF assignment to enable this option:
set_global_assignment -name ALLOW_VCCR_VCCT_PER_BANK ON

For more information about bonded configurations, refer to Channel Bonding.

Figure 153. x24 Clock Network

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