L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.1.1. ATX PLL

The ATX PLL contains LC tank-based voltage controlled oscillators (VCOs). These LC VCOs have different frequency ranges to support a continuous range of operation.

When driving the Transceiver directly, the ATX PLL only supports the integer mode. In cascade mode, the ATX PLL only supports the fractional mode.

Figure 139. ATX PLL Block Diagram

Input Reference Clock

This is the dedicated input reference clock source for the ATX PLL.

The input reference clock can be driven from one of the following sources. The sources are listed in order of performance, with the first choice giving the highest performance.

  • Dedicated reference clock pin
  • Reference clock network (with two new high quality reference clock lines)
  • Receiver input pin

The input reference clock is a differential signal. Intel® recommends using the dedicated reference clock pin as the input reference clock source for the best jitter performance. The input reference clock must be stable and free-running at device power-up for proper PLL operation and PLL calibration. If the reference clock is not available at device power-up, then you must recalibrate the PLL when the reference clock is available.

Note: The ATX PLL calibration is clocked by the OSC_CLK_1 clock, which must be stable and available for calibration to proceed. Refer to the Calibration chapter and Intel® Stratix® 10 GX, MX, and SX Device Family Pin Connection Guidelines for more details about the OSC_CLK_1 clock.

Reference Clock Multiplexer

The reference clock (refclk) multiplexer selects the reference clock to the PLL from the various reference clock sources available.

Figure 140. Reference Clock Multiplexer

N Counter

The N counter divides the refclk mux's output. The division factors supported are 1, 2, 4, and 8.

Phase Frequency Detector (PFD)

The reference clock(refclk) signal at the output of the N counter block and the feedback clock (fbclk) signal at the output of the M counter block are supplied as inputs to the PFD. The output of the PFD is proportional to the phase difference between the refclk and fbclk inputs. It is used to align the refclk signal at the output of the N counter to the feedback clock (fbclk) signal. The PFD generates an "Up" signal when the reference clock's falling edge occurs before the feedback clock's falling edge. Conversely, the PFD generates a "Down" signal when the feedback clock's falling edge occurs before the reference clock's falling edge.

Charge Pump and Loop Filter

The PFD output is used by the charge pump and loop filter (CP and LF) to generate a control voltage for the VCO. The charge pump translates the "Up" or "Down" pulses from the PFD into current pulses. The current pulses are filtered through a low pass filter into a control voltage that drives the VCO frequency. The charge pump, loop filter, and VCO settings determine the bandwidth of the ATX PLL.

Lock Detector

The lock detector block indicates when the reference clock and the feedback clock are phase aligned in integer mode, and frequency aligned in fractional mode. The lock detector generates an active high pll_locked signal to indicate that the PLL is locked to its input reference clock.

Voltage Controlled Oscillator

The voltage controlled oscillator (VCO) used in the ATX PLL is LC tank based. The output of charge pump and loop filter serves as an input to the VCO. The output frequency of the VCO depends on the input control voltage.

L Counter

The L counter divides the differential clocks generated by the ATX PLL. The L counter is not in the feedback path of the PLL.

M Counter

The M counter's output is the same frequency as the N counter's output. The VCO frequency is governed by the equation:

VCO freq = 2 * M * input reference clock/N

An additional divider divides the high speed serial clock output of the VCO by 2 before it reaches the M counter.

The M counter supports division factors in a continuous range from 8 to 127 in integer frequency synthesis mode and 11 to 123 in fractional mode.

Delta Sigma Modulator

The fractional mode is only supported when the ATX PLL is configured as a cascade source for OTN and SDI protocols. The delta sigma modulator is used in fractional mode. It modulates the M counter divide value over time so that the PLL can perform fractional frequency synthesis. In fractional mode, the M value is as follows:

M (integer) + K/232, where K is the Fractional multiply factor (K) in the ATX PLL IP Core Parameter Editor.

The legal values of K are greater than 1% and less than 99% of the full range of 232 and can only be manually entered in the ATX PLL IP Core Parameter Editor in the Intel® Quartus® Prime Pro Edition.

The output frequencies cannot be exact when the ATX PLL is configured in fractional mode. Due to the K value 32-bit resolution, translating to 1.63 Hz step for a 7 GHz VCO frequency, not all desired fractional values can be achieved exactly.

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