L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 10/05/2023
Document Table of Contents

6.16. Transceiver Register Map

The transceiver register map provides a list of available PCS, PMA, EMIB and PLL addresses that are used in the reconfiguration process.

To avoid an illegal configuration, use the register map in conjunction with a transceiver configuration file generated by the Intel® Stratix® 10 Native PHY/Transmit PLL IP core. This configuration file includes details about the registers that are set for a specific transceiver configuration. Refer to a valid transceiver configuration file for legal register values and combinations.