L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

6.9.3. Reconfiguring Between GX and GXT Channels

All GXT channels can be reconfigured to GX channels (≤ 17.4Gbps).

The receive datapath can be reconfigured by changing any of the following values in the Native PHY:

  • Changing the reference clock source
  • Changing the CDR's M/N/L counter values

The transmit datapath can be reconfigured by either of the following methods:

  • An ATX PLL drives the GXT clock lines, and a different ATX PLL/fPLL drives the GX clock lines. The Native PHY IP core has two TX clock inputs selected.
    • Change the TX serial clock source in the Native PHY IP core to select between GXT and GX datarates.
  • A single ATX PLL drives the GXT clock line and GX clock lines. Both the tx_serial_clk and tx_serial_clk_gt output ports must be enabled in the ATX PLL. The Native PHY IP core is configured to have two TX clock inputs and are connected to the serial clock ports in the ATX PLL.
    • The ATX PLL is reconfigured when switching between GXT and GX datarates. The ATX PLL needs to be recalibrated after reconfiguration.
    • The Native PHY IP core switches between the two tx_serial_clk sources.

The Native PHY IP core needs to be recalibrated if the receive or transmit datarate changes. The Native PHY recalibration must occur after the ATX PLL has locked if a single ATX PLL is used for the GXT and GX datarate for transmit (the second method above).

Note: The TX local division factor parameter in the Native PHY IP core cannot be used to switch between GXT and GX datarates when the GXT datarate is a multiple of the GX datarate.

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