L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Document Table of Contents FPGA Fabric to Transceiver Transfer

For signals that are coming from FPGA Fabric into the transceiver, there is capture logic in the transceiver which captures the signals before sending them to the shift registers.

The sampling time of the capture logic is relative to the length of the shift register chain. To ensure the signals are successfully sampled and loaded into the register chain, you must hold those signals for a minimum period of time, depending on the type of shift register chain used to transfer the signals.

Table 88.  Register Chain Minimum Hold Time Calculations
Register Chain Minimum Hold Cycles Minimum Hold Time 21
FSR 10 1.667*10 = 16.67 ns
SSR 120 1.667*120 = 200.04 ns

Given that the internal oscillator clock frequency can vary between 600 MHz and 900 MHz in the hardware, Intel recommends that you hold the signals for the worst case scenario of 600 MHz as summarized in the table above.

21 The calculation assumes an OSC divider factor of 1.

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